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bart
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FPGC6
mirror de https://github.com/bartpleiter/FPGC6
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Ramo: cpu100mhz
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FPGC6
/
Quartus
/
mainpll_sim
/
synopsys
/
vcsmx
bartpleiter 030e6c305e More tests for 100mhz há 5 meses atrás
..
synopsys_sim.setup 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. há 1 ano atrás
vcsmx_setup.sh 030e6c305e More tests for 100mhz há 5 meses atrás