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bart
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FPGC6
réplica de https://github.com/bartpleiter/FPGC6
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Rama: cpu100mhz
Ramas Etiquetas
FPGC6
/
Quartus
/
mainpll_sim
/
synopsys
/
vcsmx
bartpleiter 030e6c305e More tests for 100mhz hai 5 meses
..
synopsys_sim.setup 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
vcsmx_setup.sh 030e6c305e More tests for 100mhz hai 5 meses