Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL.

Quartus/FPGC.qsf

@@ -223,9 +223,8 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[0]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[1]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[2]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[3]
-set_global_assignment -name OPTIMIZATION_MODE BALANCED
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
 set_global_assignment -name SDC_FILE FPGC.sdc
-set_global_assignment -name QIP_FILE clkMux/synthesis/clkMux.qip
 set_global_assignment -name VERILOG_FILE modules/FPGC.v
 set_global_assignment -name VERILOG_FILE modules/Memory/L1Icache.v
 set_global_assignment -name VERILOG_FILE modules/Memory/L1Dcache.v
@@ -265,9 +264,10 @@ set_global_assignment -name VERILOG_FILE modules/Memory/ROM.v
 set_global_assignment -name VERILOG_FILE modules/Memory/MemoryUnit.v
 set_global_assignment -name VERILOG_FILE modules/MultiStabilizer.v
 set_global_assignment -name VERILOG_FILE modules/DtrReset.v
-set_global_assignment -name QIP_FILE clock_pll.qip
-set_global_assignment -name QIP_FILE NTSC_pll.qip
 set_global_assignment -name QIP_FILE ddr.qip
-set_global_assignment -name QIP_FILE clock_pll_v.qip
-set_global_assignment -name SIP_FILE clock_pll_v.sip
+set_global_assignment -name QIP_FILE mainpll.qip
+set_global_assignment -name SIP_FILE mainpll.sip
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Quartus/NTSC_pll.ppf

@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone IV E" variation_name="NTSC_pll" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="areset" direction="input" scope="external"  />
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
-<pin name="c3" direction="output" scope="external" source="clock"  />
-
-</global>
-</pinplan>

Quartus/NTSC_pll.qip

@@ -1,6 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "NTSC_pll.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "NTSC_pll_bb.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "NTSC_pll.ppf"]

Quartus/NTSC_pll.v

@@ -1,341 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: NTSC_pll.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.1 Build 850 06/23/2022 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2022  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and any partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module NTSC_pll (
-	areset,
-	inclk0,
-	c2,
-	c3);
-
-	input	  areset;
-	input	  inclk0;
-	output	  c2;
-	output	  c3;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [4:0] sub_wire0;
-	wire [0:0] sub_wire5 = 1'h0;
-	wire [3:3] sub_wire2 = sub_wire0[3:3];
-	wire [2:2] sub_wire1 = sub_wire0[2:2];
-	wire  c2 = sub_wire1;
-	wire  c3 = sub_wire2;
-	wire  sub_wire3 = inclk0;
-	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
-
-	altpll	altpll_component (
-				.areset (areset),
-				.inclk (sub_wire4),
-				.clk (sub_wire0),
-				.activeclock (),
-				.clkbad (),
-				.clkena ({6{1'b1}}),
-				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b0),
-				.enable0 (),
-				.enable1 (),
-				.extclk (),
-				.extclkena ({4{1'b1}}),
-				.fbin (1'b1),
-				.fbmimicbidir (),
-				.fbout (),
-				.fref (),
-				.icdrclk (),
-				.locked (),
-				.pfdena (1'b1),
-				.phasecounterselect ({4{1'b1}}),
-				.phasedone (),
-				.phasestep (1'b1),
-				.phaseupdown (1'b1),
-				.pllena (1'b1),
-				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
-				.scanread (1'b0),
-				.scanwrite (1'b0),
-				.sclkout0 (),
-				.sclkout1 (),
-				.vcooverrange (),
-				.vcounderrange ());
-	defparam
-		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk2_divide_by = 125,
-		altpll_component.clk2_duty_cycle = 50,
-		altpll_component.clk2_multiply_by = 63,
-		altpll_component.clk2_phase_shift = "0",
-		altpll_component.clk3_divide_by = 25,
-		altpll_component.clk3_duty_cycle = 50,
-		altpll_component.clk3_multiply_by = 63,
-		altpll_component.clk3_phase_shift = "0",
-		altpll_component.compensate_clock = "CLK2",
-		altpll_component.inclk0_input_frequency = 20000,
-		altpll_component.intended_device_family = "Cyclone IV E",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=NTSC_pll",
-		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "NORMAL",
-		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_USED",
-		altpll_component.port_clkbad0 = "PORT_UNUSED",
-		altpll_component.port_clkbad1 = "PORT_UNUSED",
-		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
-		altpll_component.port_fbin = "PORT_UNUSED",
-		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
-		altpll_component.port_locked = "PORT_UNUSED",
-		altpll_component.port_pfdena = "PORT_UNUSED",
-		altpll_component.port_phasecounterselect = "PORT_UNUSED",
-		altpll_component.port_phasedone = "PORT_UNUSED",
-		altpll_component.port_phasestep = "PORT_UNUSED",
-		altpll_component.port_phaseupdown = "PORT_UNUSED",
-		altpll_component.port_pllena = "PORT_UNUSED",
-		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
-		altpll_component.port_scanread = "PORT_UNUSED",
-		altpll_component.port_scanwrite = "PORT_UNUSED",
-		altpll_component.port_clk0 = "PORT_UNUSED",
-		altpll_component.port_clk1 = "PORT_UNUSED",
-		altpll_component.port_clk2 = "PORT_USED",
-		altpll_component.port_clk3 = "PORT_USED",
-		altpll_component.port_clk4 = "PORT_UNUSED",
-		altpll_component.port_clk5 = "PORT_UNUSED",
-		altpll_component.port_clkena0 = "PORT_UNUSED",
-		altpll_component.port_clkena1 = "PORT_UNUSED",
-		altpll_component.port_clkena2 = "PORT_UNUSED",
-		altpll_component.port_clkena3 = "PORT_UNUSED",
-		altpll_component.port_clkena4 = "PORT_UNUSED",
-		altpll_component.port_clkena5 = "PORT_UNUSED",
-		altpll_component.port_extclk0 = "PORT_UNUSED",
-		altpll_component.port_extclk1 = "PORT_UNUSED",
-		altpll_component.port_extclk2 = "PORT_UNUSED",
-		altpll_component.port_extclk3 = "PORT_UNUSED",
-		altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c2"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
-// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.200001"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "126.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "63"
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "126.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "NTSC_pll.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "63"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "25"
-// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "63"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK2"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON

Quartus/NTSC_pll_bb.v

@@ -1,228 +0,0 @@
-// megafunction wizard: %ALTPLL%VBB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: NTSC_pll.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.1 Build 850 06/23/2022 SJ Lite Edition
-// ************************************************************
-
-//Copyright (C) 2022  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and any partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-module NTSC_pll (
-	areset,
-	inclk0,
-	c2,
-	c3);
-
-	input	  areset;
-	input	  inclk0;
-	output	  c2;
-	output	  c3;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c2"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
-// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.200001"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "126.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "63"
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "126.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "NTSC_pll.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "63"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "25"
-// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "63"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK2"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON

Quartus/clkMux.qsys

@@ -1,76 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element altclkctrl_0
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="5CEFA5F23I7" />
- <parameter name="deviceFamily" value="Cyclone V" />
- <parameter name="deviceSpeedGrade" value="7" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName">Test02_project_key.qpf</parameter>
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="altclkctrl_input"
-   internal="altclkctrl_0.altclkctrl_input"
-   type="conduit"
-   dir="end">
-  <port name="inclk3x" internal="inclk3x" />
-  <port name="inclk2x" internal="inclk2x" />
-  <port name="inclk1x" internal="inclk1x" />
-  <port name="inclk0x" internal="inclk0x" />
-  <port name="clkselect" internal="clkselect" />
- </interface>
- <interface
-   name="altclkctrl_output"
-   internal="altclkctrl_0.altclkctrl_output"
-   type="conduit"
-   dir="end">
-  <port name="outclk" internal="outclk" />
- </interface>
- <module
-   name="altclkctrl_0"
-   kind="altclkctrl"
-   version="21.1"
-   enabled="1"
-   autoexport="1">
-  <parameter name="CLOCK_TYPE" value="1" />
-  <parameter name="DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="ENA_REGISTER_MODE" value="1" />
-  <parameter name="GUI_USE_ENA" value="false" />
-  <parameter name="NUMBER_OF_CLOCKS" value="4" />
-  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>

Quartus/clkMux.sopcinfo

@@ -1,281 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport name="clkMux" kind="clkMux" version="1.0" fabric="QSYS">
- <!-- Format version 21.1 850 (Future versions may contain additional information.) -->
- <!-- 2022.10.23.13:13:41 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
-  <type>java.lang.Integer</type>
-  <value>1666523621</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
-  <type>java.lang.String</type>
-  <value></value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
-  <type>java.lang.String</type>
-  <value>CYCLONEV</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
-  <type>java.lang.String</type>
-  <value>5CEFA5F23I7</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
-  <type>java.lang.String</type>
-  <value>7</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="deviceFamily">
-  <type>java.lang.String</type>
-  <value>Cyclone V</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
-  <type>boolean</type>
-  <value>false</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <module
-   name="altclkctrl_0"
-   kind="altclkctrl"
-   version="21.1"
-   path="altclkctrl_0">
-  <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
-  <parameter name="DEVICE_FAMILY">
-   <type>java.lang.String</type>
-   <value>CYCLONEV</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
-  </parameter>
-  <parameter name="CLOCK_TYPE">
-   <type>int</type>
-   <value>1</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="NUMBER_OF_CLOCKS">
-   <type>int</type>
-   <value>4</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="ENA_REGISTER_MODE">
-   <type>int</type>
-   <value>1</value>
-   <derived>false</derived>
-   <enabled>false</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="GUI_USE_ENA">
-   <type>boolean</type>
-   <value>false</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
-   <type>boolean</type>
-   <value>false</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="deviceFamily">
-   <type>java.lang.String</type>
-   <value>UNKNOWN</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="generateLegacySim">
-   <type>boolean</type>
-   <value>false</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <interface name="altclkctrl_input" kind="conduit_end" version="21.1">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>input</value>
-   </assignment>
-   <parameter name="associatedClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="associatedReset">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>conduit</type>
-   <isStart>false</isStart>
-   <port>
-    <name>inclk3x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk3x</role>
-   </port>
-   <port>
-    <name>inclk2x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk2x</role>
-   </port>
-   <port>
-    <name>inclk1x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk1x</role>
-   </port>
-   <port>
-    <name>inclk0x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk0x</role>
-   </port>
-   <port>
-    <name>clkselect</name>
-    <direction>Input</direction>
-    <width>2</width>
-    <role>clkselect</role>
-   </port>
-  </interface>
-  <interface name="altclkctrl_output" kind="conduit_end" version="21.1">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>output</value>
-   </assignment>
-   <parameter name="associatedClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="associatedReset">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>conduit</type>
-   <isStart>false</isStart>
-   <port>
-    <name>outclk</name>
-    <direction>Output</direction>
-    <width>1</width>
-    <role>outclk</role>
-   </port>
-  </interface>
- </module>
- <plugin>
-  <instanceCount>1</instanceCount>
-  <name>altclkctrl</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IModule</subtype>
-  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
-  <version>21.1</version>
- </plugin>
- <plugin>
-  <instanceCount>2</instanceCount>
-  <name>conduit_end</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
-  <displayName>Conduit</displayName>
-  <version>21.1</version>
- </plugin>
- <reportVersion>21.1 850</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>

Quartus/clkMux/clkMux.cmp

@@ -1,11 +0,0 @@
-	component clkMux is
-		port (
-			inclk3x   : in  std_logic                    := 'X';             -- inclk3x
-			inclk2x   : in  std_logic                    := 'X';             -- inclk2x
-			inclk1x   : in  std_logic                    := 'X';             -- inclk1x
-			inclk0x   : in  std_logic                    := 'X';             -- inclk0x
-			clkselect : in  std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
-			outclk    : out std_logic                                        -- outclk
-		);
-	end component clkMux;
-

Quartus/clkMux/synthesis/clkMux.debuginfo

@@ -1,363 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport name="clkMux" kind="system" version="21.1" fabric="QSYS">
- <!-- Format version 21.1 850 (Future versions may contain additional information.) -->
- <!-- 2022.10.23.13:13:42 -->
- <!-- A collection of modules and connections -->
- <parameter name="clockCrossingAdapter">
-  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
-  <value>HANDSHAKE</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="device">
-  <type>java.lang.String</type>
-  <value>5CEFA5F23I7</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
-  <type>java.lang.String</type>
-  <value>CYCLONEV</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="deviceSpeedGrade">
-  <type>java.lang.String</type>
-  <value>7</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="fabricMode">
-  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
-  <value>QSYS</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
-  <type>boolean</type>
-  <value>false</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="generationId">
-  <type>int</type>
-  <value>1666523621</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="globalResetBus">
-  <type>boolean</type>
-  <value>false</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="hdlLanguage">
-  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
-  <value>VERILOG</value>
-  <derived>false</derived>
-  <enabled>false</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="hideFromIPCatalog">
-  <type>boolean</type>
-  <value>true</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="lockedInterfaceDefinition">
-  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
-  <value></value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="maxAdditionalLatency">
-  <type>int</type>
-  <value>1</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="projectName">
-  <type>java.lang.String</type>
-  <value>Test02_project_key.qpf</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="sopcBorderPoints">
-  <type>boolean</type>
-  <value>false</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="systemHash">
-  <type>long</type>
-  <value>0</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="testBenchDutName">
-  <type>java.lang.String</type>
-  <value></value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="timeStamp">
-  <type>long</type>
-  <value>0</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <parameter name="useTestBenchNamingPattern">
-  <type>boolean</type>
-  <value>false</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
- </parameter>
- <module
-   name="altclkctrl_0"
-   kind="altclkctrl"
-   version="21.1"
-   path="altclkctrl_0">
-  <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
-  <parameter name="DEVICE_FAMILY">
-   <type>java.lang.String</type>
-   <value>CYCLONEV</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
-  </parameter>
-  <parameter name="CLOCK_TYPE">
-   <type>int</type>
-   <value>1</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="NUMBER_OF_CLOCKS">
-   <type>int</type>
-   <value>4</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="ENA_REGISTER_MODE">
-   <type>int</type>
-   <value>1</value>
-   <derived>false</derived>
-   <enabled>false</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="GUI_USE_ENA">
-   <type>boolean</type>
-   <value>false</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
-   <type>boolean</type>
-   <value>false</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="deviceFamily">
-   <type>java.lang.String</type>
-   <value>UNKNOWN</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="generateLegacySim">
-   <type>boolean</type>
-   <value>false</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <interface name="altclkctrl_input" kind="conduit_end" version="21.1">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>input</value>
-   </assignment>
-   <parameter name="associatedClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="associatedReset">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>conduit</type>
-   <isStart>false</isStart>
-   <port>
-    <name>inclk3x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk3x</role>
-   </port>
-   <port>
-    <name>inclk2x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk2x</role>
-   </port>
-   <port>
-    <name>inclk1x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk1x</role>
-   </port>
-   <port>
-    <name>inclk0x</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>inclk0x</role>
-   </port>
-   <port>
-    <name>clkselect</name>
-    <direction>Input</direction>
-    <width>2</width>
-    <role>clkselect</role>
-   </port>
-  </interface>
-  <interface name="altclkctrl_output" kind="conduit_end" version="21.1">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>output</value>
-   </assignment>
-   <parameter name="associatedClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="associatedReset">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>conduit</type>
-   <isStart>false</isStart>
-   <port>
-    <name>outclk</name>
-    <direction>Output</direction>
-    <width>1</width>
-    <role>outclk</role>
-   </port>
-  </interface>
- </module>
- <plugin>
-  <instanceCount>1</instanceCount>
-  <name>altclkctrl</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IModule</subtype>
-  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
-  <version>21.1</version>
- </plugin>
- <plugin>
-  <instanceCount>2</instanceCount>
-  <name>conduit_end</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
-  <displayName>Conduit</displayName>
-  <version>21.1</version>
- </plugin>
- <reportVersion>21.1 850</reportVersion>
- <uniqueIdentifier>8C89A553699400000184048C6ACF</uniqueIdentifier>
-</EnsembleReport>

Quartus/clkMux/synthesis/clkMux.qip

@@ -1,39 +0,0 @@
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_TOOL_VERSION "21.1"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_TOOL_ENV "Qsys"
-set_global_assignment -library "clkMux" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../clkMux.sopcinfo"]
-set_global_assignment -entity "clkMux" -library "clkMux" -name SLD_INFO "QSYS_NAME clkMux HAS_SOPCINFO 1 GENERATION_ID 1666523621"
-set_global_assignment -library "clkMux" -name MISC_FILE [file join $::quartus(qip_path) "../clkMux.cmp"]
-set_global_assignment -library "clkMux" -name SLD_FILE [file join $::quartus(qip_path) "clkMux.debuginfo"]
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "clkMux" -name MISC_FILE [file join $::quartus(qip_path) "../../clkMux.qsys"]
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_NAME "Y2xrTXV4"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_DISPLAY_NAME "Y2xrTXV4"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjUyMzYyMQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFRkE1RjIzSTc=::QXV0byBERVZJQ0U="
-set_global_assignment -entity "clkMux" -library "clkMux" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_NAME "Y2xrTXV4X2FsdGNsa2N0cmxfMA=="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_DISPLAY_NAME "QUxUQ0xLQ1RSTCBJbnRlbCBGUEdBIElQ"
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_VERSION "MjEuMQ=="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::RGV2aWNlIEZhbWlseQ=="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::NA==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24="
-
-set_global_assignment -library "clkMux" -name VERILOG_FILE [file join $::quartus(qip_path) "clkMux.v"]
-set_global_assignment -library "clkMux" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/clkMux_altclkctrl_0.v"]
-
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_TOOL_NAME "altclkctrl"
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_TOOL_VERSION "21.1"
-set_global_assignment -entity "clkMux_altclkctrl_0" -library "clkMux" -name IP_TOOL_ENV "Qsys"

Quartus/clkMux/synthesis/clkMux.v

@@ -1,24 +0,0 @@
-// clkMux.v
-
-// Generated using ACDS version 21.1 850
-
-`timescale 1 ps / 1 ps
-module clkMux (
-		input  wire       inclk3x,   //  altclkctrl_input.inclk3x
-		input  wire       inclk2x,   //                  .inclk2x
-		input  wire       inclk1x,   //                  .inclk1x
-		input  wire       inclk0x,   //                  .inclk0x
-		input  wire [1:0] clkselect, //                  .clkselect
-		output wire       outclk     // altclkctrl_output.outclk
-	);
-
-	clkMux_altclkctrl_0 altclkctrl_0 (
-		.inclk3x   (inclk3x),   //  altclkctrl_input.inclk3x
-		.inclk2x   (inclk2x),   //                  .inclk2x
-		.inclk1x   (inclk1x),   //                  .inclk1x
-		.inclk0x   (inclk0x),   //                  .inclk0x
-		.clkselect (clkselect), //                  .clkselect
-		.outclk    (outclk)     // altclkctrl_output.outclk
-	);
-
-endmodule

Quartus/clkMux/synthesis/submodules/clkMux_altclkctrl_0.v

@@ -1,136 +0,0 @@
-//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone V" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
-//VERSION_BEGIN 21.1 cbx_altclkbuf 2022:06:23:22:02:32:SJ cbx_cycloneii 2022:06:23:22:02:32:SJ cbx_lpm_add_sub 2022:06:23:22:02:32:SJ cbx_lpm_compare 2022:06:23:22:02:32:SJ cbx_lpm_decode 2022:06:23:22:02:32:SJ cbx_lpm_mux 2022:06:23:22:02:32:SJ cbx_mgl 2022:06:23:22:26:17:SJ cbx_nadder 2022:06:23:22:02:32:SJ cbx_stratix 2022:06:23:22:02:32:SJ cbx_stratixii 2022:06:23:22:02:32:SJ cbx_stratixiii 2022:06:23:22:02:32:SJ cbx_stratixv 2022:06:23:22:02:32:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-
-// Copyright (C) 2022  Intel Corporation. All rights reserved.
-//  Your use of Intel Corporation's design tools, logic functions 
-//  and other software and tools, and any partner logic 
-//  functions, and any output files from any of the foregoing 
-//  (including device programming or simulation files), and any 
-//  associated documentation or information are expressly subject 
-//  to the terms and conditions of the Intel Program License 
-//  Subscription Agreement, the Intel Quartus Prime License Agreement,
-//  the Intel FPGA IP License Agreement, or other applicable license
-//  agreement, including, without limitation, that your use is for
-//  the sole purpose of programming logic devices manufactured by
-//  Intel and sold by Intel or its authorized distributors.  Please
-//  refer to the applicable agreement for further details, at
-//  https://fpgasoftware.intel.com/eula.
-
-
-
-//synthesis_resources = cyclonev_clkena 1 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  clkMux_altclkctrl_0_sub
-	( 
-	clkselect,
-	ena,
-	inclk,
-	outclk) /* synthesis synthesis_clearbox=1 */;
-	input   [1:0]  clkselect;
-	input   ena;
-	input   [3:0]  inclk;
-	output   outclk;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0   [1:0]  clkselect;
-	tri1   ena;
-	tri0   [3:0]  inclk;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire  wire_sd2_outclk;
-	wire  wire_sd1_outclk;
-	wire  [1:0]  clkselect_wire;
-	wire  [3:0]  inclk_wire;
-
-	cyclonev_clkselect   sd2
-	( 
-	.clkselect(clkselect_wire),
-	.inclk(inclk_wire),
-	.outclk(wire_sd2_outclk));
-	cyclonev_clkena   sd1
-	( 
-	.ena(ena),
-	.enaout(),
-	.inclk(wire_sd2_outclk),
-	.outclk(wire_sd1_outclk));
-	defparam
-		sd1.clock_type = "Global Clock",
-		sd1.ena_register_mode = "always enabled",
-		sd1.lpm_type = "cyclonev_clkena";
-	assign
-		clkselect_wire = {clkselect},
-		inclk_wire = {inclk},
-		outclk = wire_sd1_outclk;
-endmodule //clkMux_altclkctrl_0_sub
-//VALID FILE // (C) 2001-2022 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files from any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Intel Program License Subscription 
-// Agreement, Intel FPGA IP License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Intel and sold by 
-// Intel or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module  clkMux_altclkctrl_0  (
-    clkselect,
-    inclk0x,
-    inclk1x,
-    inclk2x,
-    inclk3x,
-    outclk);
-
-    input  [1:0]  clkselect;
-    input    inclk0x;
-    input    inclk1x;
-    input    inclk2x;
-    input    inclk3x;
-    output   outclk;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-    tri0 [1:0]  clkselect;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-    wire  sub_wire0;
-    wire  outclk;
-    wire  sub_wire1;
-    wire  sub_wire2;
-    wire [3:0] sub_wire3;
-    wire  sub_wire4;
-    wire  sub_wire5;
-    wire  sub_wire6;
-
-    assign  outclk = sub_wire0;
-    assign  sub_wire1 = 1'h1;
-    assign  sub_wire2 = inclk0x;
-    assign sub_wire3[3:0] = {sub_wire6, sub_wire5, sub_wire4, sub_wire2};
-    assign  sub_wire4 = inclk1x;
-    assign  sub_wire5 = inclk2x;
-    assign  sub_wire6 = inclk3x;
-
-    clkMux_altclkctrl_0_sub  clkMux_altclkctrl_0_sub_component (
-                .clkselect (clkselect),
-                .ena (sub_wire1),
-                .inclk (sub_wire3),
-                .outclk (sub_wire0));
-
-endmodule

Quartus/clock_pll.ppf

@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone IV E" variation_name="clock_pll" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="areset" direction="input" scope="external"  />
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
-<pin name="c3" direction="output" scope="external" source="clock"  />
-<pin name="c4" direction="output" scope="external" source="clock"  />
-
-</global>
-</pinplan>

Quartus/clock_pll.qip

@@ -1,6 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clock_pll.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_pll_bb.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_pll.ppf"]

Quartus/clock_pll.v

@@ -1,425 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: clock_pll.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.1 Build 850 06/23/2022 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2022  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and any partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module clock_pll (
-	areset,
-	inclk0,
-	c0,
-	c1,
-	c2,
-	c3,
-	c4);
-
-	input	  areset;
-	input	  inclk0;
-	output	  c0;
-	output	  c1;
-	output	  c2;
-	output	  c3;
-	output	  c4;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [4:0] sub_wire0;
-	wire [0:0] sub_wire8 = 1'h0;
-	wire [4:4] sub_wire5 = sub_wire0[4:4];
-	wire [3:3] sub_wire4 = sub_wire0[3:3];
-	wire [2:2] sub_wire3 = sub_wire0[2:2];
-	wire [1:1] sub_wire2 = sub_wire0[1:1];
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  c1 = sub_wire2;
-	wire  c2 = sub_wire3;
-	wire  c3 = sub_wire4;
-	wire  c4 = sub_wire5;
-	wire  sub_wire6 = inclk0;
-	wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
-
-	altpll	altpll_component (
-				.areset (areset),
-				.inclk (sub_wire7),
-				.clk (sub_wire0),
-				.activeclock (),
-				.clkbad (),
-				.clkena ({6{1'b1}}),
-				.clkloss (),
-				.clkswitch (1'b0),
-				.configupdate (1'b0),
-				.enable0 (),
-				.enable1 (),
-				.extclk (),
-				.extclkena ({4{1'b1}}),
-				.fbin (1'b1),
-				.fbmimicbidir (),
-				.fbout (),
-				.fref (),
-				.icdrclk (),
-				.locked (),
-				.pfdena (1'b1),
-				.phasecounterselect ({4{1'b1}}),
-				.phasedone (),
-				.phasestep (1'b1),
-				.phaseupdown (1'b1),
-				.pllena (1'b1),
-				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
-				.scanread (1'b0),
-				.scanwrite (1'b0),
-				.sclkout0 (),
-				.sclkout1 (),
-				.vcooverrange (),
-				.vcounderrange ());
-	defparam
-		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 1,
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 2,
-		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 1,
-		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 2,
-		altpll_component.clk1_phase_shift = "5000",
-		altpll_component.clk2_divide_by = 1,
-		altpll_component.clk2_duty_cycle = 50,
-		altpll_component.clk2_multiply_by = 1,
-		altpll_component.clk2_phase_shift = "0",
-		altpll_component.clk3_divide_by = 2,
-		altpll_component.clk3_duty_cycle = 50,
-		altpll_component.clk3_multiply_by = 1,
-		altpll_component.clk3_phase_shift = "0",
-		altpll_component.clk4_divide_by = 2,
-		altpll_component.clk4_duty_cycle = 50,
-		altpll_component.clk4_multiply_by = 5,
-		altpll_component.clk4_phase_shift = "0",
-		altpll_component.compensate_clock = "CLK0",
-		altpll_component.inclk0_input_frequency = 20000,
-		altpll_component.intended_device_family = "Cyclone IV E",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clock_pll",
-		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "NORMAL",
-		altpll_component.pll_type = "AUTO",
-		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_USED",
-		altpll_component.port_clkbad0 = "PORT_UNUSED",
-		altpll_component.port_clkbad1 = "PORT_UNUSED",
-		altpll_component.port_clkloss = "PORT_UNUSED",
-		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
-		altpll_component.port_fbin = "PORT_UNUSED",
-		altpll_component.port_inclk0 = "PORT_USED",
-		altpll_component.port_inclk1 = "PORT_UNUSED",
-		altpll_component.port_locked = "PORT_UNUSED",
-		altpll_component.port_pfdena = "PORT_UNUSED",
-		altpll_component.port_phasecounterselect = "PORT_UNUSED",
-		altpll_component.port_phasedone = "PORT_UNUSED",
-		altpll_component.port_phasestep = "PORT_UNUSED",
-		altpll_component.port_phaseupdown = "PORT_UNUSED",
-		altpll_component.port_pllena = "PORT_UNUSED",
-		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
-		altpll_component.port_scanread = "PORT_UNUSED",
-		altpll_component.port_scanwrite = "PORT_UNUSED",
-		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_USED",
-		altpll_component.port_clk2 = "PORT_USED",
-		altpll_component.port_clk3 = "PORT_USED",
-		altpll_component.port_clk4 = "PORT_USED",
-		altpll_component.port_clk5 = "PORT_UNUSED",
-		altpll_component.port_clkena0 = "PORT_UNUSED",
-		altpll_component.port_clkena1 = "PORT_UNUSED",
-		altpll_component.port_clkena2 = "PORT_UNUSED",
-		altpll_component.port_clkena3 = "PORT_UNUSED",
-		altpll_component.port_clkena4 = "PORT_UNUSED",
-		altpll_component.port_clkena5 = "PORT_UNUSED",
-		altpll_component.port_extclk0 = "PORT_UNUSED",
-		altpll_component.port_extclk1 = "PORT_UNUSED",
-		altpll_component.port_extclk2 = "PORT_UNUSED",
-		altpll_component.port_extclk3 = "PORT_UNUSED",
-		altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "125.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "25.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "125.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock_pll.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "5"
-// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON

Quartus/clock_pll_bb.v

@@ -1,294 +0,0 @@
-// megafunction wizard: %ALTPLL%VBB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll 
-
-// ============================================================
-// File Name: clock_pll.v
-// Megafunction Name(s):
-// 			altpll
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.1 Build 850 06/23/2022 SJ Lite Edition
-// ************************************************************
-
-//Copyright (C) 2022  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and any partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-module clock_pll (
-	areset,
-	inclk0,
-	c0,
-	c1,
-	c2,
-	c3,
-	c4);
-
-	input	  areset;
-	input	  inclk0;
-	output	  c0;
-	output	  c1;
-	output	  c2;
-	output	  c3;
-	output	  c4;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "125.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "25.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "125.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock_pll.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "5"
-// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON

Quartus/clock_pll_v.qip

@@ -1,337 +0,0 @@
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_TOOL_VERSION "21.1"
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_TOOL_ENV "mwpim"
-set_global_assignment -library "clock_pll_v" -name MISC_FILE [file join $::quartus(qip_path) "clock_pll_v.cmp"]
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_QSYS_MODE "UNKNOWN"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_COMPONENT_NAME "Y2xvY2tfcGxsX3Y="
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_COMPONENT_VERSION "MjEuMQ=="
-set_global_assignment -entity "clock_pll_v" -library "clock_pll_v" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_NAME "Y2xvY2tfcGxsX3ZfMDAwMg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_VERSION "MjEuMQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTI1LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::NQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MjUwMA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::OTAuMA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjUuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTI1LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MjUwMCBwcw==::cGhhc2Vfc2hpZnQz"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::NTAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw1LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwxMCwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyLDIsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMywyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsMywyLDIsMixwaF9tdXhfY2xrLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDIsMjAsNDAwMCw1MDAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLGZhbHNl::UGFyYW1ldGVyIFZhbHVlcw=="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
-
-set_global_assignment -library "clock_pll_v" -name VERILOG_FILE [file join $::quartus(qip_path) "clock_pll_v.v"]
-set_global_assignment -library "clock_pll_v" -name VERILOG_FILE [file join $::quartus(qip_path) "clock_pll_v/clock_pll_v_0002.v"]
-set_global_assignment -library "clock_pll_v" -name QIP_FILE [file join $::quartus(qip_path) "clock_pll_v/clock_pll_v_0002.qip"]
-
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_TOOL_VERSION "21.1"
-set_global_assignment -entity "clock_pll_v_0002" -library "clock_pll_v" -name IP_TOOL_ENV "mwpim"

Quartus/clock_pll_v.sip

@@ -1,6 +0,0 @@
-set_global_assignment -entity "clock_pll_v" -library "lib_clock_pll_v" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "clock_pll_v" -library "lib_clock_pll_v" -name IP_TOOL_VERSION "21.1"
-set_global_assignment -entity "clock_pll_v" -library "lib_clock_pll_v" -name IP_TOOL_ENV "mwpim"
-set_global_assignment -library "lib_clock_pll_v" -name SPD_FILE [file join $::quartus(sip_path) "clock_pll_v.spd"]
-
-set_global_assignment -library "lib_clock_pll_v" -name MISC_FILE [file join $::quartus(sip_path) "clock_pll_v_sim/clock_pll_v.vo"]

Quartus/clock_pll_v/clock_pll_v_0002.qip

@@ -1,4 +0,0 @@
-set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*clock_pll_v_0002*|altera_pll:altera_pll_i*|*"
- 
-set_instance_assignment -name PLL_AUTO_RESET OFF -to "*clock_pll_v_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*clock_pll_v_0002*|altera_pll:altera_pll_i*|*"

Quartus/clock_pll_v_sim/clock_pll_v.vo

@@ -1,309 +0,0 @@
-//IP Functional Simulation Model
-//VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-
-// Copyright (C) 2022  Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions 
-// and other software and tools, and any partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Intel Program License 
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors.  Please
-// refer to the applicable agreement for further details, at
-// https://fpgasoftware.intel.com/eula.
-
-// You may only use these simulation model output files for simulation
-// purposes and expressly not for synthesis or any other purposes (in which
-// event Intel disclaims all warranties of any kind).
-
-
-//synopsys translate_off
-
-//synthesis_resources = altera_pll 1 
-`timescale 1 ps / 1 ps
-module  clock_pll_v
-	( 
-	locked,
-	outclk_0,
-	outclk_1,
-	outclk_2,
-	outclk_3,
-	outclk_4,
-	refclk,
-	rst) /* synthesis synthesis_clearbox=1 */;
-	output   locked;
-	output   outclk_0;
-	output   outclk_1;
-	output   outclk_2;
-	output   outclk_3;
-	output   outclk_4;
-	input   refclk;
-	input   rst;
-
-	wire  wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked;
-	wire  [4:0]   wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk;
-
-	altera_pll   clock_pll_v_altera_pll_altera_pll_i_2475
-	( 
-	.fbclk(1'b0),
-	.locked(wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked),
-	.outclk(wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk),
-	.refclk(refclk),
-	.rst(rst));
-	defparam
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en0 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en1 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en10 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en11 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en12 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en13 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en14 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en15 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en16 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en17 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en2 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en3 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en4 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en5 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en6 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en7 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en8 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en9 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div0 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div1 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div10 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div11 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div12 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div13 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div14 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div15 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div16 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div17 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div2 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div3 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div4 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div5 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div6 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div7 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div8 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div9 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src0 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src1 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src10 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src11 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src12 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src13 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src14 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src15 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src16 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src17 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src2 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src3 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src4 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src5 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src6 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src7 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src8 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src9 = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div0 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div1 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div10 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div11 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div12 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div13 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div14 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div15 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div16 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div17 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div2 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div3 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div4 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div5 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div6 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div7 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div8 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div9 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en0 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en1 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en10 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en11 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en12 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en13 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en14 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en15 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en16 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en17 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en2 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en3 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en4 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en5 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en6 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en7 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en8 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en9 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst0 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst1 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst10 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst11 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst12 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst13 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst14 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst15 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst16 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst17 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst2 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst3 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst4 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst5 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst6 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst7 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst8 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst9 = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst0 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst1 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst10 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst11 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst12 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst13 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst14 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst15 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst16 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst17 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst2 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst3 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst4 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst5 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst6 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst7 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst8 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst9 = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_0 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_1 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_2 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_3 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_4 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_5 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_6 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_7 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_8 = "UNUSED",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_0 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_1 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_2 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_3 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_4 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_5 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_6 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_7 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_8 = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.data_rate = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.deserialization_factor = 4,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle0 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle1 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle10 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle11 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle12 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle13 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle14 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle15 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle16 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle17 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle2 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle3 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle4 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle5 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle6 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle7 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle8 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle9 = 50,
-		clock_pll_v_altera_pll_altera_pll_i_2475.fractional_vco_multiplier = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_bypass_en = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_hi_div = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_lo_div = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_odd_div_duty_en = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.mimic_fbclk_type = "gclk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_bypass_en = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_hi_div = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_lo_div = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_odd_div_duty_en = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.number_of_clocks = 5,
-		clock_pll_v_altera_pll_altera_pll_i_2475.operation_mode = "direct",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency0 = "25.000000 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency1 = "125.000000 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency10 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency11 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency12 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency13 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency14 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency15 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency16 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency17 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency2 = "100.000000 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency3 = "100.000000 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency4 = "50.000000 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency5 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency6 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency7 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency8 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency9 = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift0 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift1 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift10 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift11 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift12 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift13 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift14 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift15 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift16 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift17 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift2 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift3 = "2500 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift4 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift5 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift6 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift7 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift8 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift9 = "0 ps",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_auto_clk_sw_en = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_bw_sel = "low",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_bwctrl = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clk_loss_sw_en = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clk_sw_dly = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clkin_0_src = "clk_0",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clkin_1_src = "clk_0",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_cp_current = 0,
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_dsm_out_sel = "1st_order",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fbclk_mux_1 = "glb",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fbclk_mux_2 = "fb_1",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fractional_cout = 24,
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fractional_division = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_m_cnt_in_src = "ph_mux_clk",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_manu_clk_sw_en = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_output_clk_frequency = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_slf_rst = "false",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_subtype = "General",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_type = "General",
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_vco_div = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.pll_vcoph_div = 1,
-		clock_pll_v_altera_pll_altera_pll_i_2475.refclk1_frequency = "0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.reference_clock_frequency = "50.0 MHz",
-		clock_pll_v_altera_pll_altera_pll_i_2475.sim_additional_refclk_cycles_to_lock = 0;
-	assign
-		locked = wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked,
-		outclk_0 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[0],
-		outclk_1 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[1],
-		outclk_2 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[2],
-		outclk_3 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[3],
-		outclk_4 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[4];
-endmodule //clock_pll_v
-//synopsys translate_on
-//VALID FILE

Quartus/mainpll.bsf

@@ -0,0 +1,115 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 264)
+	(text "mainpll" (rect 60 -1 85 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 248 20 260)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
+		(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 48 112)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
+		(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 112 72)(line_width 1))
+	)
+	(port
+		(pt 160 112)
+		(output)
+		(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
+		(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
+		(line (pt 160 112)(pt 112 112)(line_width 1))
+	)
+	(port
+		(pt 160 152)
+		(output)
+		(text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8)))
+		(text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8)))
+		(line (pt 160 152)(pt 112 152)(line_width 1))
+	)
+	(port
+		(pt 160 192)
+		(output)
+		(text "outclk_3" (rect 0 0 33 12)(font "Arial" (font_size 8)))
+		(text "outclk_3" (rect 117 181 165 192)(font "Arial" (font_size 8)))
+		(line (pt 160 192)(pt 112 192)(line_width 1))
+	)
+	(port
+		(pt 160 232)
+		(output)
+		(text "outclk_4" (rect 0 0 34 12)(font "Arial" (font_size 8)))
+		(text "outclk_4" (rect 117 221 165 232)(font "Arial" (font_size 8)))
+		(line (pt 160 232)(pt 112 232)(line_width 1))
+	)
+	(drawing
+		(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
+		(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
+		(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
+		(text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0)))
+		(text "outclk3" (rect 113 163 268 339)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 187 212 384)(font "Arial" (color 0 0 0)))
+		(text "outclk4" (rect 113 203 268 419)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 227 212 464)(font "Arial" (color 0 0 0)))
+		(text " altera_pll " (rect 118 248 308 506)(font "Arial" ))
+		(line (pt 48 32)(pt 112 32)(line_width 1))
+		(line (pt 112 32)(pt 112 248)(line_width 1))
+		(line (pt 48 248)(pt 112 248)(line_width 1))
+		(line (pt 48 32)(pt 48 248)(line_width 1))
+		(line (pt 49 52)(pt 49 76)(line_width 1))
+		(line (pt 50 52)(pt 50 76)(line_width 1))
+		(line (pt 49 92)(pt 49 116)(line_width 1))
+		(line (pt 50 92)(pt 50 116)(line_width 1))
+		(line (pt 111 52)(pt 111 76)(line_width 1))
+		(line (pt 110 52)(pt 110 76)(line_width 1))
+		(line (pt 111 92)(pt 111 116)(line_width 1))
+		(line (pt 110 92)(pt 110 116)(line_width 1))
+		(line (pt 111 132)(pt 111 156)(line_width 1))
+		(line (pt 110 132)(pt 110 156)(line_width 1))
+		(line (pt 111 172)(pt 111 196)(line_width 1))
+		(line (pt 110 172)(pt 110 196)(line_width 1))
+		(line (pt 111 212)(pt 111 236)(line_width 1))
+		(line (pt 110 212)(pt 110 236)(line_width 1))
+		(line (pt 0 0)(pt 160 0)(line_width 1))
+		(line (pt 160 0)(pt 160 264)(line_width 1))
+		(line (pt 0 264)(pt 160 264)(line_width 1))
+		(line (pt 0 0)(pt 0 264)(line_width 1))
+	)
+)

Quartus/clock_pll_v.cmp → Quartus/mainpll.cmp

@@ -1,4 +1,4 @@
-	component clock_pll_v is
+	component mainpll is
 		port (
 			refclk   : in  std_logic := 'X'; -- clk
 			rst      : in  std_logic := 'X'; -- reset
@@ -8,5 +8,5 @@
 			outclk_3 : out std_logic;        -- clk
 			outclk_4 : out std_logic         -- clk
 		);
-	end component clock_pll_v;
+	end component mainpll;
 

Quartus/mainpll.ppf

@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="mainpll"
+ megafunction_name="ALTERA_PLL"
+ intended_family="Cyclone V"
+ specifies="all_ports">
+ <global>
+  <pin name="refclk" direction="input" scope="external" />
+  <pin name="rst" direction="input" scope="external" />
+  <pin name="outclk_0" direction="output" scope="external" />
+  <pin name="outclk_1" direction="output" scope="external" />
+  <pin name="outclk_2" direction="output" scope="external" />
+  <pin name="outclk_3" direction="output" scope="external" />
+  <pin name="outclk_4" direction="output" scope="external" />
+ </global>
+</pinplan>

Quartus/mainpll.qip

@@ -0,0 +1,337 @@
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "mainpll" -name MISC_FILE [file join $::quartus(qip_path) "mainpll.cmp"]
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_NAME "bWFpbnBsbA=="
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_NAME "bWFpbnBsbF8wMDAy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTI1LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::NA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::NTAwMCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NTAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MjUuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MTI1LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw1LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDIsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwzLDIsMyw0LHBoX211eF9jbGssZmFsc2UsdHJ1ZSw1LDUsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTAsMTAsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDIsMjAsNDAwMCw1MDAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLGZhbHNl::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "mainpll" -name VERILOG_FILE [file join $::quartus(qip_path) "mainpll.v"]
+set_global_assignment -library "mainpll" -name VERILOG_FILE [file join $::quartus(qip_path) "mainpll/mainpll_0002.v"]
+set_global_assignment -library "mainpll" -name QIP_FILE [file join $::quartus(qip_path) "mainpll/mainpll_0002.qip"]
+
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_TOOL_ENV "mwpim"

Quartus/mainpll.sip

@@ -0,0 +1,6 @@
+set_global_assignment -entity "mainpll" -library "lib_mainpll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "mainpll" -library "lib_mainpll" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "mainpll" -library "lib_mainpll" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_mainpll" -name SPD_FILE [file join $::quartus(sip_path) "mainpll.spd"]
+
+set_global_assignment -library "lib_mainpll" -name MISC_FILE [file join $::quartus(sip_path) "mainpll_sim/mainpll.vo"]

Quartus/clock_pll_v.spd → Quartus/mainpll.spd

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <simPackage>
- <file path="clock_pll_v_sim/clock_pll_v.vo" type="VERILOG" />
- <topLevel name="clock_pll_v" />
+ <file path="mainpll_sim/mainpll.vo" type="VERILOG" />
+ <topLevel name="mainpll" />
  <deviceFamily name="cyclonev" />
 </simPackage>

Quartus/clock_pll_v.v → Quartus/mainpll.v

@@ -1,11 +1,11 @@
 // megafunction wizard: %PLL Intel FPGA IP v21.1%
 // GENERATION: XML
-// clock_pll_v.v
+// mainpll.v
 
 // Generated using ACDS version 21.1 850
 
 `timescale 1 ps / 1 ps
-module clock_pll_v (
+module mainpll (
 		input  wire  refclk,   //  refclk.clk
 		input  wire  rst,      //   reset.reset
 		output wire  outclk_0, // outclk0.clk
@@ -15,7 +15,7 @@ module clock_pll_v (
 		output wire  outclk_4  // outclk4.clk
 	);
 
-	clock_pll_v_0002 clock_pll_v_inst (
+	mainpll_0002 mainpll_inst (
 		.refclk   (refclk),   //  refclk.clk
 		.rst      (rst),      //   reset.reset
 		.outclk_0 (outclk_0), // outclk0.clk
@@ -33,7 +33,7 @@ endmodule
 //	************************************************************
 //	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //	************************************************************
-//	Copyright (C) 1991-2022 Altera Corporation
+//	Copyright (C) 1991-2023 Altera Corporation
 //	Any megafunction design, and related net list (encrypted or decrypted),
 //	support information, device programming or simulation file, and any other
 //	associated documentation or information provided by Altera or a partner
@@ -73,46 +73,46 @@ endmodule
 // Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
 // Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
 // Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="25.0" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="100.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+// Retrieval info: 	<generic name="gui_ps_units0" value="degrees" />
 // Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
 // Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
 // Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="125.0" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="100.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+// Retrieval info: 	<generic name="gui_ps_units1" value="degrees" />
 // Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="180.0" />
 // Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="50.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+// Retrieval info: 	<generic name="gui_ps_units2" value="degrees" />
 // Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
 // Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
 // Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="25.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
 // Retrieval info: 	<generic name="gui_ps_units3" value="degrees" />
-// Retrieval info: 	<generic name="gui_phase_shift3" value="2500" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="90.0" />
+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
 // Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="50.0" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="125.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+// Retrieval info: 	<generic name="gui_ps_units4" value="degrees" />
 // Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
 // Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
 // Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
@@ -256,5 +256,5 @@ endmodule
 // Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
 // Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
 // Retrieval info: </instance>
-// IPFS_FILES : clock_pll_v.vo
-// RELATED_FILES: clock_pll_v.v, clock_pll_v_0002.v
+// IPFS_FILES : mainpll.vo
+// RELATED_FILES: mainpll.v, mainpll_0002.v

Quartus/mainpll/mainpll_0002.qip

@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*mainpll_0002*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mainpll_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mainpll_0002*|altera_pll:altera_pll_i*|*"

Quartus/clock_pll_v/clock_pll_v_0002.v → Quartus/mainpll/mainpll_0002.v

@@ -1,5 +1,5 @@
 `timescale 1ns/10ps
-module  clock_pll_v_0002(
+module  mainpll_0002(
 
 	// interface 'refclk'
 	input wire refclk,
@@ -31,19 +31,19 @@ module  clock_pll_v_0002(
 		.reference_clock_frequency("50.0 MHz"),
 		.operation_mode("direct"),
 		.number_of_clocks(5),
-		.output_clock_frequency0("25.000000 MHz"),
+		.output_clock_frequency0("100.000000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
-		.output_clock_frequency1("125.000000 MHz"),
-		.phase_shift1("0 ps"),
+		.output_clock_frequency1("100.000000 MHz"),
+		.phase_shift1("5000 ps"),
 		.duty_cycle1(50),
-		.output_clock_frequency2("100.000000 MHz"),
+		.output_clock_frequency2("50.000000 MHz"),
 		.phase_shift2("0 ps"),
 		.duty_cycle2(50),
-		.output_clock_frequency3("100.000000 MHz"),
-		.phase_shift3("2500 ps"),
+		.output_clock_frequency3("25.000000 MHz"),
+		.phase_shift3("0 ps"),
 		.duty_cycle3(50),
-		.output_clock_frequency4("50.000000 MHz"),
+		.output_clock_frequency4("125.000000 MHz"),
 		.phase_shift4("0 ps"),
 		.duty_cycle4(50),
 		.output_clock_frequency5("0 MHz"),

Quartus/mainpll_sim.f

@@ -0,0 +1 @@
+mainpll_sim/mainpll.vo

Quartus/mainpll_sim/aldec/rivierapro_setup.tcl

@@ -0,0 +1,278 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     mainpll
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If mainpll is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "mainpll"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/bart/intelFPGA_lite/21.1/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib                       ./libraries/altera_ver           
+vmap       altera_ver            ./libraries/altera_ver           
+ensure_lib                       ./libraries/lpm_ver              
+vmap       lpm_ver               ./libraries/lpm_ver              
+ensure_lib                       ./libraries/sgate_ver            
+vmap       sgate_ver             ./libraries/sgate_ver            
+ensure_lib                       ./libraries/altera_mf_ver        
+vmap       altera_mf_ver         ./libraries/altera_mf_ver        
+ensure_lib                       ./libraries/altera_lnsim_ver     
+vmap       altera_lnsim_ver      ./libraries/altera_lnsim_ver     
+ensure_lib                       ./libraries/cyclonev_ver         
+vmap       cyclonev_ver          ./libraries/cyclonev_ver         
+ensure_lib                       ./libraries/cyclonev_hssi_ver    
+vmap       cyclonev_hssi_ver     ./libraries/cyclonev_hssi_ver    
+ensure_lib                       ./libraries/cyclonev_pcie_hip_ver
+vmap       cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                    -work altera_ver           
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                             -work lpm_ver              
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                -work sgate_ver            
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                            -work altera_mf_ver        
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                        -work altera_lnsim_ver     
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                       -work cyclonev_ver         
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                  -work cyclonev_hssi_ver    
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"              -work cyclonev_pcie_hip_ver
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/mainpll.vo"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h

Quartus/mainpll_sim/cadence/cds.lib

@@ -0,0 +1,19 @@
+
+DEFINE std                   $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys              $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee                  $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit                 $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory          $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils               $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal            $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels              $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions        $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work                  ./libraries/work/                         
+DEFINE altera_ver            ./libraries/altera_ver/                   
+DEFINE lpm_ver               ./libraries/lpm_ver/                      
+DEFINE sgate_ver             ./libraries/sgate_ver/                    
+DEFINE altera_mf_ver         ./libraries/altera_mf_ver/                
+DEFINE altera_lnsim_ver      ./libraries/altera_lnsim_ver/             
+DEFINE cyclonev_ver          ./libraries/cyclonev_ver/                 
+DEFINE cyclonev_hssi_ver     ./libraries/cyclonev_hssi_ver/            
+DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/        

Quartus/mainpll_sim/cadence/hdl.var

@@ -0,0 +1,2 @@
+
+DEFINE WORK work

Quartus/mainpll_sim/cadence/ncsim_setup.sh

@@ -0,0 +1,195 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     mainpll
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If mainpll is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="mainpll"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                      -work altera_ver           
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                               -work lpm_ver              
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                  -work sgate_ver            
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                              -work altera_mf_ver        
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                          -work altera_lnsim_ver     
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                         -work cyclonev_ver         
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                    -work cyclonev_hssi_ver    
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"                -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/mainpll.vo"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  export GENERIC_PARAM_COMPAT_CHECK=1
+  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

Quartus/mainpll_sim/mainpll.vo

@@ -0,0 +1,309 @@
+//IP Functional Simulation Model
+//VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2022  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// You may only use these simulation model output files for simulation
+// purposes and expressly not for synthesis or any other purposes (in which
+// event Intel disclaims all warranties of any kind).
+
+
+//synopsys translate_off
+
+//synthesis_resources = altera_pll 1 
+`timescale 1 ps / 1 ps
+module  mainpll
+	( 
+	locked,
+	outclk_0,
+	outclk_1,
+	outclk_2,
+	outclk_3,
+	outclk_4,
+	refclk,
+	rst) /* synthesis synthesis_clearbox=1 */;
+	output   locked;
+	output   outclk_0;
+	output   outclk_1;
+	output   outclk_2;
+	output   outclk_3;
+	output   outclk_4;
+	input   refclk;
+	input   rst;
+
+	wire  wire_mainpll_altera_pll_altera_pll_i_2475_locked;
+	wire  [4:0]   wire_mainpll_altera_pll_altera_pll_i_2475_outclk;
+
+	altera_pll   mainpll_altera_pll_altera_pll_i_2475
+	( 
+	.fbclk(1'b0),
+	.locked(wire_mainpll_altera_pll_altera_pll_i_2475_locked),
+	.outclk(wire_mainpll_altera_pll_altera_pll_i_2475_outclk),
+	.refclk(refclk),
+	.rst(rst));
+	defparam
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en0 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en1 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en10 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en11 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en12 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en13 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en14 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en15 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en16 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en17 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en2 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en3 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en4 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en5 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en6 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en7 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en8 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en9 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div0 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div1 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div10 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div11 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div12 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div13 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div14 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div15 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div16 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div17 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div2 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div3 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div4 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div5 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div6 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div7 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div8 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div9 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src0 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src1 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src10 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src11 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src12 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src13 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src14 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src15 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src16 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src17 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src2 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src3 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src4 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src5 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src6 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src7 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src8 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src9 = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div0 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div1 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div10 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div11 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div12 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div13 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div14 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div15 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div16 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div17 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div2 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div3 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div4 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div5 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div6 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div7 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div8 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div9 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en0 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en1 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en10 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en11 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en12 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en13 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en14 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en15 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en16 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en17 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en2 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en3 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en4 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en5 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en6 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en7 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en8 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en9 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst0 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst1 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst10 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst11 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst12 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst13 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst14 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst15 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst16 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst17 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst2 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst3 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst4 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst5 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst6 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst7 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst8 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst9 = 0,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst0 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst1 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst10 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst11 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst12 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst13 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst14 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst15 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst16 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst17 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst2 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst3 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst4 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst5 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst6 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst7 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst8 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst9 = 1,
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_0 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_1 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_2 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_3 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_4 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_5 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_6 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_7 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_8 = "UNUSED",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_0 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_1 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_2 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_3 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_4 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_5 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_6 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_7 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.clock_name_global_8 = "false",
+		mainpll_altera_pll_altera_pll_i_2475.data_rate = 0,
+		mainpll_altera_pll_altera_pll_i_2475.deserialization_factor = 4,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle0 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle1 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle10 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle11 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle12 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle13 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle14 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle15 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle16 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle17 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle2 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle3 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle4 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle5 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle6 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle7 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle8 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.duty_cycle9 = 50,
+		mainpll_altera_pll_altera_pll_i_2475.fractional_vco_multiplier = "false",
+		mainpll_altera_pll_altera_pll_i_2475.m_cnt_bypass_en = "false",
+		mainpll_altera_pll_altera_pll_i_2475.m_cnt_hi_div = 1,
+		mainpll_altera_pll_altera_pll_i_2475.m_cnt_lo_div = 1,
+		mainpll_altera_pll_altera_pll_i_2475.m_cnt_odd_div_duty_en = "false",
+		mainpll_altera_pll_altera_pll_i_2475.mimic_fbclk_type = "gclk",
+		mainpll_altera_pll_altera_pll_i_2475.n_cnt_bypass_en = "false",
+		mainpll_altera_pll_altera_pll_i_2475.n_cnt_hi_div = 1,
+		mainpll_altera_pll_altera_pll_i_2475.n_cnt_lo_div = 1,
+		mainpll_altera_pll_altera_pll_i_2475.n_cnt_odd_div_duty_en = "false",
+		mainpll_altera_pll_altera_pll_i_2475.number_of_clocks = 5,
+		mainpll_altera_pll_altera_pll_i_2475.operation_mode = "direct",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency0 = "100.000000 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency1 = "100.000000 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency10 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency11 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency12 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency13 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency14 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency15 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency16 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency17 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency2 = "50.000000 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency3 = "25.000000 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency4 = "125.000000 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency5 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency6 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency7 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency8 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency9 = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift0 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift1 = "5000 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift10 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift11 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift12 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift13 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift14 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift15 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift16 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift17 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift2 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift3 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift4 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift5 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift6 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift7 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift8 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.phase_shift9 = "0 ps",
+		mainpll_altera_pll_altera_pll_i_2475.pll_auto_clk_sw_en = "false",
+		mainpll_altera_pll_altera_pll_i_2475.pll_bw_sel = "low",
+		mainpll_altera_pll_altera_pll_i_2475.pll_bwctrl = 0,
+		mainpll_altera_pll_altera_pll_i_2475.pll_clk_loss_sw_en = "false",
+		mainpll_altera_pll_altera_pll_i_2475.pll_clk_sw_dly = 0,
+		mainpll_altera_pll_altera_pll_i_2475.pll_clkin_0_src = "clk_0",
+		mainpll_altera_pll_altera_pll_i_2475.pll_clkin_1_src = "clk_0",
+		mainpll_altera_pll_altera_pll_i_2475.pll_cp_current = 0,
+		mainpll_altera_pll_altera_pll_i_2475.pll_dsm_out_sel = "1st_order",
+		mainpll_altera_pll_altera_pll_i_2475.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
+		mainpll_altera_pll_altera_pll_i_2475.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss",
+		mainpll_altera_pll_altera_pll_i_2475.pll_fbclk_mux_1 = "glb",
+		mainpll_altera_pll_altera_pll_i_2475.pll_fbclk_mux_2 = "fb_1",
+		mainpll_altera_pll_altera_pll_i_2475.pll_fractional_cout = 24,
+		mainpll_altera_pll_altera_pll_i_2475.pll_fractional_division = 1,
+		mainpll_altera_pll_altera_pll_i_2475.pll_m_cnt_in_src = "ph_mux_clk",
+		mainpll_altera_pll_altera_pll_i_2475.pll_manu_clk_sw_en = "false",
+		mainpll_altera_pll_altera_pll_i_2475.pll_output_clk_frequency = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.pll_slf_rst = "false",
+		mainpll_altera_pll_altera_pll_i_2475.pll_subtype = "General",
+		mainpll_altera_pll_altera_pll_i_2475.pll_type = "General",
+		mainpll_altera_pll_altera_pll_i_2475.pll_vco_div = 1,
+		mainpll_altera_pll_altera_pll_i_2475.pll_vcoph_div = 1,
+		mainpll_altera_pll_altera_pll_i_2475.refclk1_frequency = "0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.reference_clock_frequency = "50.0 MHz",
+		mainpll_altera_pll_altera_pll_i_2475.sim_additional_refclk_cycles_to_lock = 0;
+	assign
+		locked = wire_mainpll_altera_pll_altera_pll_i_2475_locked,
+		outclk_0 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[0],
+		outclk_1 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[1],
+		outclk_2 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[2],
+		outclk_3 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[3],
+		outclk_4 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[4];
+endmodule //mainpll
+//synopsys translate_on
+//VALID FILE

Quartus/mainpll_sim/mentor/msim_setup.tcl

@@ -0,0 +1,272 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     mainpll
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If mainpll is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "mainpll"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/bart/intelFPGA_lite/21.1/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
+  ensure_lib                       ./libraries/altera_ver/           
+  vmap       altera_ver            ./libraries/altera_ver/           
+  ensure_lib                       ./libraries/lpm_ver/              
+  vmap       lpm_ver               ./libraries/lpm_ver/              
+  ensure_lib                       ./libraries/sgate_ver/            
+  vmap       sgate_ver             ./libraries/sgate_ver/            
+  ensure_lib                       ./libraries/altera_mf_ver/        
+  vmap       altera_mf_ver         ./libraries/altera_mf_ver/        
+  ensure_lib                       ./libraries/altera_lnsim_ver/     
+  vmap       altera_lnsim_ver      ./libraries/altera_lnsim_ver/     
+  ensure_lib                       ./libraries/cyclonev_ver/         
+  vmap       cyclonev_ver          ./libraries/cyclonev_ver/         
+  ensure_lib                       ./libraries/cyclonev_hssi_ver/    
+  vmap       cyclonev_hssi_ver     ./libraries/cyclonev_hssi_ver/    
+  ensure_lib                       ./libraries/cyclonev_pcie_hip_ver/
+  vmap       cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                     -work altera_ver           
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                              -work lpm_ver              
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                 -work sgate_ver            
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                             -work altera_mf_ver        
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                         -work altera_lnsim_ver     
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                        -work cyclonev_ver         
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                   -work cyclonev_hssi_ver    
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"               -work cyclonev_pcie_hip_ver
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/mainpll.vo"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h

Quartus/mainpll_sim/synopsys/vcs/vcs_setup.sh

@@ -0,0 +1,152 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+
+# ----------------------------------------
+# vcs - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     mainpll
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, follow the guidelines below.
+# 
+# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
+# below into a new file, e.g. named "vcs_sim.sh".
+# 
+# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
+# a separate file, e.g. named "filelist.f".
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
+# # set the top-level simulation or testbench module/entity name.
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# # Source the Quartus-generated IP simulation script and do the following:
+# # - Compile the Quartus EDA simulation library and IP simulation files.
+# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
+# # - Compile the design and top-level simulation module/entity using
+# #   information specified in "filelist.f".
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# # - Run the simulation.
+# #
+# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
+# TOP_LEVEL_NAME=<simulation top> \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# ----------------------------------------
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the Quartus-generated IP simulation script)
+# #
+# +systemverilogext+.sv
+# <design and testbench files, compile-time options, elaboration options>
+# #
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If mainpll is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="mainpll"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
+  $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
+  $QSYS_SIMDIR/mainpll.vo \
+  -top $TOP_LEVEL_NAME
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

Quartus/mainpll_sim/synopsys/vcsmx/synopsys_sim.setup

@@ -0,0 +1,13 @@
+
+WORK > DEFAULT
+DEFAULT:               ./libraries/work/                 
+work:                  ./libraries/work/                 
+altera_ver:            ./libraries/altera_ver/           
+lpm_ver:               ./libraries/lpm_ver/              
+sgate_ver:             ./libraries/sgate_ver/            
+altera_mf_ver:         ./libraries/altera_mf_ver/        
+altera_lnsim_ver:      ./libraries/altera_lnsim_ver/     
+cyclonev_ver:          ./libraries/cyclonev_ver/         
+cyclonev_hssi_ver:     ./libraries/cyclonev_hssi_ver/    
+cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
+LIBRARY_SCAN = TRUE

Quartus/mainpll_sim/synopsys/vcsmx/vcsmx_setup.sh

@@ -0,0 +1,195 @@
+
+# (C) 2001-2023 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     mainpll
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries 
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If mainpll is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="mainpll"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                       -work altera_ver           
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                                -work lpm_ver              
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                   -work sgate_ver            
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                               -work altera_mf_ver        
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                           -work altera_lnsim_ver     
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                          -work cyclonev_ver         
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                     -work cyclonev_hssi_ver    
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"                 -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/mainpll.vo"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

Quartus/modules/FPGC.v

@@ -119,6 +119,7 @@ wire clk;               // System clock                         (50MHz)
 //.outclk_4     (clk)
 //);
 
+/*
 clock_pll clkPll(
 .inclk0 (clock),
 .areset (1'b0),
@@ -128,6 +129,17 @@ clock_pll clkPll(
 .c3     (clkPixel),
 .c4     (clkTMDShalf)
 );
+*/
+
+mainpll mainClkPll(
+.refclk      (clock),
+.rst  		 (1'b0),
+.outclk_0     (clk_SDRAM),
+.outclk_1     (SDRAM_CLK),
+.outclk_2     (clk),
+.outclk_3     (clkPixel),
+.outclk_4     (clkTMDShalf)
+);
 
 wire clk14; //14.31818MHz (50*63/220)
 wire clk114; //14.31818 * 8 MHz = 114.5454MHz (50*(63*2)/55)