bart/FPGC6 @ da2bff2ea263a9293dce5b26cbe66ebfeffbc40b

镜像来自 https://github.com/bartpleiter/FPGC6

bart e1bb01a621 Cleaned and renamed Quartus project.		1 年之前
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clock_pll_v.vo	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 年之前