bart/FPGC6 @ 82a433530cab7d5ff6f3b8844206a20da672f663

bart 82a433530c Reverted L2 cache size to 1024 words for easier debugging.		1 년 전
..
clkMux	e1bb01a621 Cleaned and renamed Quartus project.	2 년 전
clock_pll_v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
clock_pll_v_sim	e1bb01a621 Cleaned and renamed Quartus project.	2 년 전
memory	7e81e7fa17 Added files missing from last commit (L1I cache).	1 년 전
modules	82a433530c Reverted L2 cache size to 1024 words for easier debugging.	1 년 전
output_files	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
FPGC.qpf	e1bb01a621 Cleaned and renamed Quartus project.	2 년 전
FPGC.qsf	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
FPGC.qws	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
FPGC.sdc	e1bb01a621 Cleaned and renamed Quartus project.	2 년 전
NTSC_pll.ppf	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
NTSC_pll.qip	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 년 전
NTSC_pll.v	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
NTSC_pll_bb.v	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
clkMux.qsys	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
clkMux.sopcinfo	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
clock_pll.ppf	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
clock_pll.qip	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 년 전
clock_pll.v	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
clock_pll_bb.v	da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.	1 년 전
clock_pll_v.cmp	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
clock_pll_v.qip	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
clock_pll_v.sip	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
clock_pll_v.spd	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
clock_pll_v.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
ddr.ppf	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
ddr.qip	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
ddr.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
ddr_bb.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 년 전
output_file.cof	e1bb01a621 Cleaned and renamed Quartus project.	2 년 전