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zrcadlo https://github.com/bartpleiter/FPGC6
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FPGC6
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Quartus
bart 82a433530c Reverted L2 cache size to 1024 words for easier debugging. před 1 rokem
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clkMux e1bb01a621 Cleaned and renamed Quartus project. před 1 rokem
clock_pll_v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
clock_pll_v_sim e1bb01a621 Cleaned and renamed Quartus project. před 1 rokem
memory 7e81e7fa17 Added files missing from last commit (L1I cache). před 1 rokem
modules 82a433530c Reverted L2 cache size to 1024 words for easier debugging. před 1 rokem
output_files da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
FPGC.qpf e1bb01a621 Cleaned and renamed Quartus project. před 1 rokem
FPGC.qsf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
FPGC.qws da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
FPGC.sdc e1bb01a621 Cleaned and renamed Quartus project. před 1 rokem
NTSC_pll.ppf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
NTSC_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram před 2 roky
NTSC_pll.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
NTSC_pll_bb.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
clkMux.qsys a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
clkMux.sopcinfo a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
clock_pll.ppf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
clock_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram před 2 roky
clock_pll.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
clock_pll_bb.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. před 1 rokem
clock_pll_v.cmp a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
clock_pll_v.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
clock_pll_v.sip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
clock_pll_v.spd a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
clock_pll_v.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
ddr.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
ddr.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
ddr.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
ddr_bb.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
output_file.cof e1bb01a621 Cleaned and renamed Quartus project. před 1 rokem