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bart
/
FPGC6
mirrorاز https://github.com/bartpleiter/FPGC6
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درخت: 82a433530c
شاخه‌ها تگ‌ها
FPGC6
/
Quartus
bart 82a433530c Reverted L2 cache size to 1024 words for easier debugging. 1 سال پیش
..
clkMux e1bb01a621 Cleaned and renamed Quartus project. 1 سال پیش
clock_pll_v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v_sim e1bb01a621 Cleaned and renamed Quartus project. 1 سال پیش
memory 7e81e7fa17 Added files missing from last commit (L1I cache). 1 سال پیش
modules 82a433530c Reverted L2 cache size to 1024 words for easier debugging. 1 سال پیش
output_files da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
FPGC.qpf e1bb01a621 Cleaned and renamed Quartus project. 1 سال پیش
FPGC.qsf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
FPGC.qws da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
FPGC.sdc e1bb01a621 Cleaned and renamed Quartus project. 1 سال پیش
NTSC_pll.ppf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
NTSC_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 سال پیش
NTSC_pll.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
NTSC_pll_bb.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
clkMux.qsys a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clkMux.sopcinfo a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll.ppf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
clock_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 سال پیش
clock_pll.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
clock_pll_bb.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 سال پیش
clock_pll_v.cmp a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.sip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.spd a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr_bb.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
output_file.cof e1bb01a621 Cleaned and renamed Quartus project. 1 سال پیش