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FPGC6
zrkadlo https://github.com/bartpleiter/FPGC6
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Strom: 69d109e653
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FPGC6
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Quartus
bart 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 rok pred
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mainpll 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll_sim 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
memory 7e81e7fa17 Added files missing from last commit (L1I cache). 1 rok pred
modules 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 rok pred
output_files 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 rok pred
FPGC.qpf e1bb01a621 Cleaned and renamed Quartus project. 1 rok pred
FPGC.qsf 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 rok pred
FPGC.qws 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 rok pred
FPGC.sdc e1bb01a621 Cleaned and renamed Quartus project. 1 rok pred
ddr.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 rokov pred
ddr.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 rokov pred
ddr.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 rokov pred
ddr_bb.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 rokov pred
mainpll.bsf 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll.cmp 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll.ppf 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll.qip 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll.sip 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll.spd 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll.v 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
mainpll_sim.f 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 rok pred
output_file.cof e1bb01a621 Cleaned and renamed Quartus project. 1 rok pred