bart 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. hai 1 ano
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mainpll 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll_sim 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
memory 7e81e7fa17 Added files missing from last commit (L1I cache). hai 1 ano
modules 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. hai 1 ano
output_files 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. hai 1 ano
FPGC.qpf e1bb01a621 Cleaned and renamed Quartus project. hai 1 ano
FPGC.qsf 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. hai 1 ano
FPGC.qws 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. hai 1 ano
FPGC.sdc e1bb01a621 Cleaned and renamed Quartus project. hai 1 ano
ddr.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. %!s(int64=2) %!d(string=hai) anos
ddr.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. %!s(int64=2) %!d(string=hai) anos
ddr.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. %!s(int64=2) %!d(string=hai) anos
ddr_bb.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. %!s(int64=2) %!d(string=hai) anos
mainpll.bsf 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll.cmp 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll.ppf 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll.qip 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll.sip 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll.spd 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll.v 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
mainpll_sim.f 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. hai 1 ano
output_file.cof e1bb01a621 Cleaned and renamed Quartus project. hai 1 ano