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bart
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FPGC6
mirror de https://github.com/bartpleiter/FPGC6
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Ramo: cpu100mhz
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FPGC6
/
Quartus
/
mainpll_sim
/
cadence
bart 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. há 1 ano atrás
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cds.lib 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. há 1 ano atrás
hdl.var 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. há 1 ano atrás
ncsim_setup.sh 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. há 1 ano atrás