e5dd555fdbRegister forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.
2 年之前
Bart
a76e895a39Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
2 年之前
Bart
55f619efaeInitial commit with some empty Verilog template code from FPGC5
Bart