コミット履歴

作者 SHA1 メッセージ 日付
  Bart e5dd555fdb Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation. 2 年 前
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. 2 年 前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年 前