bart/FPGC6

espejo de https://github.com/bartpleiter/FPGC6

Autor	SHA1 Mensaje	Fecha
Bart	e5dd555fdb Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.	hace 2 años
Bart	a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.	hace 2 años
Bart	55f619efae Initial commit with some empty Verilog template code from FPGC5	hace 2 años