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Auteur SHA1 Message Date
  Bart e5dd555fdb Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation. il y a 2 ans
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. il y a 2 ans
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 il y a 2 ans