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The SDRAM is used as the main memory for the FPGC. It has a size of 64MiB (2x32MiB). Since it is SDRAM, it requires a controller that handles all access and refreshes. The SDRAM controller is used to interface with the SDRAM. During initialization, the chip is set to a CAS latency of 2 and a programmable burst length of 1 (since we have 32 bit words, and the SDRAM bus is also 32 bits). The controller also handles refreshes. The controller returns the CPU bus as fast as possible to allow the CPU do other things while the controller is still busy with e.g. writing a word. The data of the SDRAM at power up is undefined, but probably zero. Note that during a reset (soft or hard) of the FPGC, the contents of the SDRAM (but not the cache!) will stay. To clear the contents of the SDRAM, you can either write all addresses with zeros, or power down the FPGC for several seconds.


I also added a simulation model of the SDRAM to the project. The currently used SDRAM chip is the Winbond W9825G6KH-6, and the FPGA module uses two of these. An older revision of the FPGA development board uses the Micron MT48LC16M16A2 chip. As I originally started with this chip, and since it appears to be a drop-in replacement anyways, I still use the Verilog SDRAM simulation model from the Micron chip.