Skip to content


The CPU has an extendable amount of interrupt pins (as of writing 10 enabled and 8 in use). The interrupt controller detects rising edges for each interrupt pin and handles them one at a time, with higher priority for lower pin numbers. If the CPU has interrupts disabled (because it might be in one already or the system is not ready yet), then the interrupts will be processed when the CPU has them enabled again. This way the CPU will not miss any, unless a new one triggers before the previous one on the same pin was sent to the CPU.

When the CPU handles an interrupt, it will disable interrupts, save the PC and jump to address 0x01. Then, the interrupt ID (which corresponds to the interrupt number) can de obtained using the INTID instruction. During the interrupt the registers are not stored automatically, so to prevent corrupting the running code, it is recommended to push all registers to the stack at the start of the interrupt handler, and restoring them before the RETI instruction. After a RETI instruction, interrupts will be enabled again and the CPU will jump to the saved PC.