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CPU
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2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
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1 anno fa |
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GPU
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 anno fa |
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IO
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 anni fa |
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Memory
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f78729ea77
Fixed L2 cache state machine issue which was only present in the previous commit.
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1 anno fa |
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DtrReset.v
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 anni fa |
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FPGC.v
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9294ee0605
Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL.
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1 anno fa |
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MultiStabilizer.v
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 anni fa |
bart
9294ee0605
Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL.