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bart
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FPGC6
réplica de https://github.com/bartpleiter/FPGC6
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FPGC6
/
Quartus
/
clock_pll_v_sim
bart e1bb01a621 Cleaned and renamed Quartus project. hai 1 ano
..
clock_pll_v.vo a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. %!s(int64=2) %!d(string=hai) anos