| .. |
|
FPDivider.v
|
69d109e653
Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions.
|
há 1 ano atrás |
|
IDivider.v
|
69d109e653
Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions.
|
há 1 ano atrás |
|
Keyboard.v
|
916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
|
há 2 anos atrás |
|
LEDvisualizer.v
|
916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
|
há 2 anos atrás |
|
MillisCounter.v
|
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
|
há 1 ano atrás |
|
NESpadReader.v
|
916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
|
há 2 anos atrás |
|
OStimer.v
|
916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
|
há 2 anos atrás |
|
SimpleSPI.v
|
916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
|
há 2 anos atrás |
|
UARTrx.v
|
916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
|
há 2 anos atrás |
|
UARTtx.v
|
916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
|
há 2 anos atrás |
bart
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.