bart 0fd222280a Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps. 1 rok temu
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FPDivider.v 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 rok temu
IDivider.v 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 rok temu
Keyboard.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 lat temu
LEDvisualizer.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 lat temu
MillisCounter.v 0fd222280a Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps. 1 rok temu
NESpadReader.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 lat temu
OStimer.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 lat temu
SimpleSPI.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 lat temu
UARTrx.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 lat temu
UARTtx.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 lat temu