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FPGC6
spegling av https://github.com/bartpleiter/FPGC6
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Gren: fast-cpu-pipeline
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FPGC6
/
Quartus
/
mainpll_sim
/
mentor
bart 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 år sedan
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msim_setup.tcl 9294ee0605 Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL. 1 år sedan