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FPGC6
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FPGC6
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Quartus
bart f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 anno fa
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clkMux e1bb01a621 Cleaned and renamed Quartus project. 1 anno fa
clock_pll_v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
clock_pll_v_sim e1bb01a621 Cleaned and renamed Quartus project. 1 anno fa
memory 7e81e7fa17 Added files missing from last commit (L1I cache). 1 anno fa
modules f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 anno fa
output_files f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 anno fa
FPGC.qpf e1bb01a621 Cleaned and renamed Quartus project. 1 anno fa
FPGC.qsf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 anno fa
FPGC.qws f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 anno fa
FPGC.sdc e1bb01a621 Cleaned and renamed Quartus project. 1 anno fa
NTSC_pll.ppf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 anno fa
NTSC_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 anni fa
NTSC_pll.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 anno fa
NTSC_pll_bb.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 anno fa
clkMux.qsys a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
clkMux.sopcinfo a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
clock_pll.ppf da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 anno fa
clock_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 anni fa
clock_pll.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 anno fa
clock_pll_bb.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 anno fa
clock_pll_v.cmp a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
clock_pll_v.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
clock_pll_v.sip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
clock_pll_v.spd a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
clock_pll_v.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
ddr.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
ddr.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
ddr.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
ddr_bb.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 anni fa
output_file.cof e1bb01a621 Cleaned and renamed Quartus project. 1 anno fa