bart f3f3a43044 Added fixed-point signed divider to MU. Integrated into FPCALC. пре 1 година
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CPU 3af9eecaa9 Added signed fixed point multiplication to ALU. пре 1 година
GPU da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. пре 1 година
IO f3f3a43044 Added fixed-point signed divider to MU. Integrated into FPCALC. пре 1 година
Memory f3f3a43044 Added fixed-point signed divider to MU. Integrated into FPCALC. пре 1 година
DtrReset.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram пре 2 година
FPGC6.v da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. пре 1 година
MultiStabilizer.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram пре 2 година