bart 52f2819774 Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future. 1 tahun lalu
..
compileROM.sh 9662964536 Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done. 2 tahun lalu
flash.py b6831c4209 Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency. 1 tahun lalu
flasher_accurate.bin 8d56c91fea Added fast (but inaccurate) and accurate (but slow) option for UART flasher. 2 tahun lalu
flasher_fast.bin 52f2819774 Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future. 1 tahun lalu
netFlash.py 9f74a9565f Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again! 2 tahun lalu
netUpload.py 9f74a9565f Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again! 2 tahun lalu
sendCommand.py 9f74a9565f Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again! 2 tahun lalu
uartFlasher.py b6831c4209 Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency. 1 tahun lalu