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compileROM.sh
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9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
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il y a 2 ans |
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flash.py
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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il y a 1 an |
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flasher_accurate.bin
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8d56c91fea
Added fast (but inaccurate) and accurate (but slow) option for UART flasher.
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il y a 2 ans |
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flasher_fast.bin
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52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
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il y a 1 an |
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netFlash.py
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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il y a 2 ans |
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netUpload.py
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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il y a 2 ans |
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sendCommand.py
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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il y a 2 ans |
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uartFlasher.py
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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il y a 1 an |
bart
52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.