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bart
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FPGC6
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https://github.com/bartpleiter/FPGC6
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EP4CE15
cpu100mhz
fast-cpu-pipeline
main
FPGC6
/
Quartus
/
mainpll_sim
/
aldec
bart
9294ee0605
Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL.
1 ano atrás
..
rivierapro_setup.tcl
9294ee0605
Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL.
1 ano atrás