bartpleiter 030e6c305e More tests for 100mhz 5 mesiacov pred
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B32P.gtkw 69e83fb855 Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline. 2 rokov pred
FPGC.gtkw 030e6c305e More tests for 100mhz 5 mesiacov pred
FPGC_50.gtkw 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. 5 mesiacov pred
FSX.gtkw 6e3cd7cd9c PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs. 1 rok pred
SDRAM.gtkw 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 rok pred
divider.gtkw f3f3a43044 Added fixed-point signed divider to MU. Integrated into FPCALC. 1 rok pred