bartpleiter 030e6c305e More tests for 100mhz 6 months ago
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CPU 030e6c305e More tests for 100mhz 6 months ago
GPU 0fd222280a Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps. 1 year ago
IO 0fd222280a Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps. 1 year ago
Memory 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. 6 months ago
DtrReset.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago
FPGC6.v 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. 6 months ago
MultiStabilizer.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago