MemoryUnit.v 1.4 KB

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  1. /*
  2. * Memory Unit
  3. */
  4. module MemoryUnit(
  5. // Clocks
  6. input clk,
  7. input reset,
  8. // Bus
  9. input [26:0] bus_addr,
  10. input [31:0] bus_data,
  11. input bus_we,
  12. input bus_start,
  13. output [31:0] bus_q,
  14. output reg bus_done = 1'b0
  15. );
  16. reg bus_done_next = 1'b0;
  17. //---------------------------SRAM---------------------------------
  18. //SRAM I/O
  19. wire sram_cpu_clk;
  20. wire [11:0] sram_cpu_addr;
  21. wire [31:0] sram_cpu_d;
  22. wire sram_cpu_we;
  23. wire [31:0] sram_cpu_q;
  24. assign sram_cpu_addr = bus_addr;
  25. assign sram_cpu_d = bus_data;
  26. assign sram_cpu_we = bus_we;
  27. assign bus_q = sram_cpu_q;
  28. SRAM #(
  29. .WIDTH(32),
  30. .WORDS(4096),
  31. .ADDR_BITS(12),
  32. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/sram.list")
  33. ) sram(
  34. //CPU port
  35. .cpu_clk (clk),
  36. .cpu_d (sram_cpu_d),
  37. .cpu_addr (sram_cpu_addr),
  38. .cpu_we (sram_cpu_we),
  39. .cpu_q (sram_cpu_q)
  40. );
  41. always @(posedge clk)
  42. begin
  43. if (reset)
  44. begin
  45. bus_done <= 1'b0;
  46. bus_done_next <= 1'b0;
  47. end
  48. else
  49. begin
  50. if (bus_done_next)
  51. begin
  52. bus_done_next <= 1'b0;
  53. bus_done <= 1'b1;
  54. end
  55. else
  56. begin
  57. bus_done <= 1'b0;
  58. if (bus_start)
  59. begin
  60. if (!bus_done_next) bus_done_next <= 1'b1;
  61. end
  62. end
  63. end
  64. end
  65. endmodule