bart/FPGC6 @ cpu100mhz

bartpleiter 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench.		vor 4 Monaten
..
CPU_arch.jpg	9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench.	vor 4 Monaten
PCB_back.png	442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done.	vor 1 Jahr
PCB_front.png	442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done.	vor 1 Jahr
complete_no_ext.jpg	442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done.	vor 1 Jahr
gtkwave.png	c1486c43e0 Documentation update. Remove subl3 files.	vor 4 Monaten
logo_big_alpha.png	3d9b4194f7 Added initial documentation	vor 2 Jahren
render.jpg	442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done.	vor 1 Jahr
schematic.png	442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done.	vor 1 Jahr
soldered.jpg	442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done.	vor 1 Jahr
vvp.png	c1486c43e0 Documentation update. Remove subl3 files.	vor 4 Monaten