simulate.sh 509 B

123456789
  1. # Build script for assembly files for simulation in verilog (run from SRAM)
  2. if (python3 Assembler.py bdos 0x000000 > ../Verilog/memory/sram.list) # compile and write to verilog memory folder
  3. then
  4. iverilog -o /home/bart/Documents/FPGA/FPGC6/Verilog/output/output /home/bart/Documents/FPGA/FPGC6/Verilog/testbench/FPGC_100MHz_tb.v
  5. vvp /home/bart/Documents/FPGA/FPGC6/Verilog/output/output
  6. else
  7. # print the error, which is in code.list
  8. (cat ../Verilog/memory/sram.list)
  9. fi