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SDRAM_tb.v 3.1 KB

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  1. /*
  2. * Testbench
  3. * Simulation for the new SDRAM controller
  4. */
  5. // Set timescale
  6. `timescale 1 ns/1 ns
  7. // Includes
  8. // Memory
  9. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/mt48lc16m16a2.v"
  10. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SDRAMcontroller.v"
  11. // Define testmodule
  12. module SDRAM_tb;
  13. // clock/reset I/O
  14. reg clk = 1'b0;
  15. reg reset = 1'b0;
  16. /////////
  17. //SDRAM
  18. /////////
  19. wire SDRAM_CLK; // SDRAM clock
  20. wire [31 : 0] SDRAM_DQ; // SDRAM I/O
  21. wire [12 : 0] SDRAM_A; // SDRAM Address
  22. wire [1 : 0] SDRAM_BA; // Bank Address
  23. wire SDRAM_CKE; // Synchronous Clock Enable
  24. wire SDRAM_CSn; // CS#
  25. wire SDRAM_RASn; // RAS#
  26. wire SDRAM_CASn; // CAS#
  27. wire SDRAM_WEn; // WE#
  28. wire [3 : 0] SDRAM_DQM; // Mask
  29. assign SDRAM_CLK = ~clk;
  30. mt48lc16m16a2 sdram1 (
  31. .Dq (SDRAM_DQ[15:0]),
  32. .Addr (SDRAM_A),
  33. .Ba (SDRAM_BA),
  34. .Clk (SDRAM_CLK),
  35. .Cke (SDRAM_CKE),
  36. .Cs_n (SDRAM_CSn),
  37. .Ras_n (SDRAM_RASn),
  38. .Cas_n (SDRAM_CASn),
  39. .We_n (SDRAM_WEn),
  40. .Dqm (SDRAM_DQM[1:0])
  41. );
  42. mt48lc16m16a2 sdram2 (
  43. .Dq (SDRAM_DQ[31:16]),
  44. .Addr (SDRAM_A),
  45. .Ba (SDRAM_BA),
  46. .Clk (SDRAM_CLK),
  47. .Cke (SDRAM_CKE),
  48. .Cs_n (SDRAM_CSn),
  49. .Ras_n (SDRAM_RASn),
  50. .Cas_n (SDRAM_CASn),
  51. .We_n (SDRAM_WEn),
  52. .Dqm (SDRAM_DQM[3:2])
  53. );
  54. ////////////////////
  55. //SDRAM Controller
  56. ////////////////////
  57. // inputs
  58. reg [23:0] sdc_addr = 24'd0; // address to write or to start reading from
  59. reg [31:0] sdc_data = 32'd0; // data to write
  60. reg sdc_we = 1'b0; // write enable
  61. reg sdc_start = 1'b0; // start trigger
  62. // outputs
  63. wire [31:0] sdc_q; // memory output
  64. wire sdc_done; // output ready
  65. SDRAMcontroller sdramcontroller(
  66. // clock/reset inputs
  67. .clk (clk),
  68. .reset (reset),
  69. // interface inputs
  70. .sdc_addr (sdc_addr),
  71. .sdc_data (sdc_data),
  72. .sdc_we (sdc_we),
  73. .sdc_start (sdc_start),
  74. // interface outputs
  75. .sdc_q (sdc_q),
  76. .sdc_done (sdc_done),
  77. // SDRAM signals
  78. .SDRAM_CKE (SDRAM_CKE),
  79. .SDRAM_CSn (SDRAM_CSn),
  80. .SDRAM_WEn (SDRAM_WEn),
  81. .SDRAM_CASn (SDRAM_CASn),
  82. .SDRAM_RASn (SDRAM_RASn),
  83. .SDRAM_A (SDRAM_A),
  84. .SDRAM_BA (SDRAM_BA),
  85. .SDRAM_DQM (SDRAM_DQM),
  86. .SDRAM_DQ (SDRAM_DQ)
  87. );
  88. initial
  89. begin
  90. // dump everything for GTKwave
  91. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  92. $dumpvars;
  93. clk = 1'b0;
  94. reset = 1'b0;
  95. #10
  96. // startup
  97. repeat(120)
  98. begin
  99. clk = ~clk;
  100. #10 clk = ~clk;
  101. #10;
  102. end
  103. // write
  104. sdc_addr = 24'd21;
  105. sdc_data = 32'hABCDEF23;
  106. sdc_we = 1'b1;
  107. sdc_start = 1'b1; // stays high until done received
  108. repeat(6)
  109. begin
  110. clk = ~clk;
  111. #10 clk = ~clk;
  112. #10;
  113. end
  114. sdc_data = 32'd0;
  115. sdc_we = 1'b0;
  116. repeat(30)
  117. begin
  118. clk = ~clk;
  119. #10 clk = ~clk;
  120. #10;
  121. end
  122. #1 $finish;
  123. end
  124. endmodule