bartpleiter c1486c43e0 Documentation update. Remove subl3 files. 6 months ago
..
B32P_tb.v b6831c4209 Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency. 1 year ago
FPGC_tb.v c1486c43e0 Documentation update. Remove subl3 files. 6 months ago
FSX_tb.v 6e3cd7cd9c PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs. 1 year ago
SDRAM_tb.v 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 year ago
divider_tb.v 69d109e653 Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions. 1 year ago