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B32P_tb.v 14 KB

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  1. /*
  2. * Testbench
  3. * Simulates the B32P CPU
  4. */
  5. // Set timescale
  6. `timescale 1 ns/1 ns
  7. // Include modules
  8. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/CPU.v"
  9. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ALU.v"
  10. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ControlUnit.v"
  11. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstructionDecoder.v"
  12. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regbank.v"
  13. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Stack.v"
  14. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstrMem.v"
  15. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/DataMem.v"
  16. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regr.v"
  17. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/IntController.v"
  18. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Arbiter.v"
  19. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/VRAM.v"
  20. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/mt48lc16m16a2.v"
  21. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/w25q128jv.v"
  22. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SDRAMcontroller.v"
  23. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SPIreader.v"
  24. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/ROM.v"
  25. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/MemoryUnit.v"
  26. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/Keyboard.v"
  27. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/OStimer.v"
  28. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/UARTtx.v"
  29. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/UARTrx.v"
  30. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/SimpleSPI.v"
  31. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/LEDvisualizer.v"
  32. // Define testmodule
  33. module B32P_tb;
  34. //---------------CPU----------------
  35. // CPU I/O
  36. reg clk = 0;
  37. reg clk_SDRAM = 0;
  38. reg reset = 0;
  39. reg int1 = 1'b0;
  40. reg int2 = 1'b0;
  41. reg int3 = 1'b0;
  42. reg int4 = 1'b0;
  43. reg int5 = 1'b0;
  44. reg int6 = 1'b0;
  45. reg int7 = 1'b0;
  46. reg int8 = 1'b0;
  47. reg int9 = 1'b0;
  48. reg int10 = 1'b0;
  49. //Bus
  50. wire [26:0] bus_addr;
  51. wire [31:0] bus_data;
  52. wire bus_we;
  53. wire bus_start;
  54. wire [31:0] bus_q;
  55. wire bus_done;
  56. //----------DEV-------------
  57. //---------------------------VRAM32---------------------------------
  58. //VRAM32 I/O
  59. wire vram32_gpu_clk;
  60. wire [13:0] vram32_gpu_addr;
  61. wire [31:0] vram32_gpu_d;
  62. wire vram32_gpu_we;
  63. wire [31:0] vram32_gpu_q;
  64. wire vram32_cpu_clk;
  65. wire [13:0] vram32_cpu_addr;
  66. wire [31:0] vram32_cpu_d;
  67. wire vram32_cpu_we;
  68. wire [31:0] vram32_cpu_q;
  69. //because FSX will not write to VRAM
  70. assign vram32_gpu_we = 1'b0;
  71. assign vram32_gpu_d = 32'd0;
  72. VRAM #(
  73. .WIDTH(32),
  74. .WORDS(1056),
  75. .LIST("/home/bart/Documents/FPGA/FPGC5/Verilog/memory/vram32.list")
  76. ) vram32(
  77. //CPU port
  78. .cpu_clk (clk),
  79. .cpu_d (vram32_cpu_d),
  80. .cpu_addr (vram32_cpu_addr),
  81. .cpu_we (vram32_cpu_we),
  82. .cpu_q (vram32_cpu_q),
  83. //GPU port
  84. .gpu_clk (clkMuxOut),
  85. .gpu_d (vram32_gpu_d),
  86. .gpu_addr (vram32_gpu_addr),
  87. .gpu_we (vram32_gpu_we),
  88. .gpu_q (vram32_gpu_q)
  89. );
  90. //---------------------------VRAM322--------------------------------
  91. //VRAM322 I/O
  92. wire vram322_gpu_clk;
  93. wire [13:0] vram322_gpu_addr;
  94. wire [31:0] vram322_gpu_d;
  95. wire vram322_gpu_we;
  96. wire [31:0] vram322_gpu_q;
  97. //because FSX will not write to VRAM
  98. assign vram322_gpu_we = 1'b0;
  99. assign vram322_gpu_d = 32'd0;
  100. VRAM #(
  101. .WIDTH(32),
  102. .WORDS(1056),
  103. .LIST("/home/bart/Documents/FPGA/FPGC5/Verilog/memory/vram32.list")
  104. ) vram322(
  105. //CPU port
  106. .cpu_clk (clk),
  107. .cpu_d (vram32_cpu_d),
  108. .cpu_addr (vram32_cpu_addr),
  109. .cpu_we (vram32_cpu_we),
  110. .cpu_q (),
  111. //GPU port
  112. .gpu_clk (clkMuxOut),
  113. .gpu_d (vram322_gpu_d),
  114. .gpu_addr (vram322_gpu_addr),
  115. .gpu_we (vram322_gpu_we),
  116. .gpu_q (vram322_gpu_q)
  117. );
  118. //--------------------------VRAM8--------------------------------
  119. //VRAM8 I/O
  120. wire vram8_gpu_clk;
  121. wire [13:0] vram8_gpu_addr;
  122. wire [7:0] vram8_gpu_d;
  123. wire vram8_gpu_we;
  124. wire [7:0] vram8_gpu_q;
  125. wire vram8_cpu_clk;
  126. wire [13:0] vram8_cpu_addr;
  127. wire [7:0] vram8_cpu_d;
  128. wire vram8_cpu_we;
  129. wire [7:0] vram8_cpu_q;
  130. //because FSX will not write to VRAM
  131. assign vram8_gpu_we = 1'b0;
  132. assign vram8_gpu_d = 8'd0;
  133. VRAM #(
  134. .WIDTH(8),
  135. .WORDS(8194),
  136. .LIST("/home/bart/Documents/FPGA/FPGC5/Verilog/memory/vram8.list")
  137. ) vram8(
  138. //CPU port
  139. .cpu_clk (clk),
  140. .cpu_d (vram8_cpu_d),
  141. .cpu_addr (vram8_cpu_addr),
  142. .cpu_we (vram8_cpu_we),
  143. .cpu_q (vram8_cpu_q),
  144. //GPU port
  145. .gpu_clk (clkMuxOut),
  146. .gpu_d (vram8_gpu_d),
  147. .gpu_addr (vram8_gpu_addr),
  148. .gpu_we (vram8_gpu_we),
  149. .gpu_q (vram8_gpu_q)
  150. );
  151. //--------------------------VRAMSPR--------------------------------
  152. //VRAMSPR I/O
  153. wire vramSPR_gpu_clk;
  154. wire [13:0] vramSPR_gpu_addr;
  155. wire [8:0] vramSPR_gpu_d;
  156. wire vramSPR_gpu_we;
  157. wire [8:0] vramSPR_gpu_q;
  158. wire vramSPR_cpu_clk;
  159. wire [13:0] vramSPR_cpu_addr;
  160. wire [8:0] vramSPR_cpu_d;
  161. wire vramSPR_cpu_we;
  162. wire [8:0] vramSPR_cpu_q;
  163. //because FSX will not write to VRAM
  164. assign vramSPR_gpu_we = 1'b0;
  165. assign vramSPR_gpu_d = 9'd0;
  166. VRAM #(
  167. .WIDTH(9),
  168. .WORDS(256),
  169. .LIST("/home/bart/Documents/FPGA/FPGC5/Verilog/memory/vramSPR.list")
  170. ) vramSPR(
  171. //CPU port
  172. .cpu_clk (clk),
  173. .cpu_d (vramSPR_cpu_d),
  174. .cpu_addr (vramSPR_cpu_addr),
  175. .cpu_we (vramSPR_cpu_we),
  176. .cpu_q (vramSPR_cpu_q),
  177. //GPU port
  178. .gpu_clk (clkMuxOut),
  179. .gpu_d (vramSPR_gpu_d),
  180. .gpu_addr (vramSPR_gpu_addr),
  181. .gpu_we (vramSPR_gpu_we),
  182. .gpu_q (vramSPR_gpu_q)
  183. );
  184. //-------------------ROM-------------------------
  185. //ROM I/O
  186. wire [8:0] rom_addr;
  187. wire [31:0] rom_q;
  188. ROM rom(
  189. .clk (clk),
  190. .reset (reset),
  191. .address (rom_addr),
  192. .q (rom_q)
  193. );
  194. //SPI0 Flash
  195. wire SPI0_clk;
  196. wire SPI0_cs;
  197. wire SPI0_data;
  198. wire SPI0_wp;
  199. wire SPI0_q;
  200. wire SPI0_hold;
  201. W25Q128JV spiFlash (
  202. .CLK (SPI0_clk),
  203. .DIO (SPI0_data),
  204. .CSn (SPI0_cs),
  205. .WPn (SPI0_wp),
  206. .HOLDn (SPI0_hold),
  207. .DO (SPI0_q)
  208. );
  209. //SDRAM
  210. wire SDRAM_CLK; // SDRAM clock
  211. wire [31 : 0] SDRAM_DQ; // SDRAM I/O
  212. wire [12 : 0] SDRAM_A; // SDRAM Address
  213. wire [1 : 0] SDRAM_BA; // Bank Address
  214. wire SDRAM_CKE; // Synchronous Clock Enable
  215. wire SDRAM_CSn; // CS#
  216. wire SDRAM_RASn; // RAS#
  217. wire SDRAM_CASn; // CAS#
  218. wire SDRAM_WEn; // WE#
  219. wire [3 : 0] SDRAM_DQM; // Mask
  220. assign SDRAM_CLK = clk_SDRAM;
  221. mt48lc16m16a2 sdram1 (
  222. .Dq (SDRAM_DQ[15:0]),
  223. .Addr (SDRAM_A),
  224. .Ba (SDRAM_BA),
  225. .Clk (SDRAM_CLK),
  226. .Cke (SDRAM_CKE),
  227. .Cs_n (SDRAM_CSn),
  228. .Ras_n (SDRAM_RASn),
  229. .Cas_n (SDRAM_CASn),
  230. .We_n (SDRAM_WEn),
  231. .Dqm (SDRAM_DQM[1:0])
  232. );
  233. mt48lc16m16a2 sdram2 (
  234. .Dq (SDRAM_DQ[31:16]),
  235. .Addr (SDRAM_A),
  236. .Ba (SDRAM_BA),
  237. .Clk (SDRAM_CLK),
  238. .Cke (SDRAM_CKE),
  239. .Cs_n (SDRAM_CSn),
  240. .Ras_n (SDRAM_RASn),
  241. .Cas_n (SDRAM_CASn),
  242. .We_n (SDRAM_WEn),
  243. .Dqm (SDRAM_DQM[3:2])
  244. );
  245. //----------------SDRAM Controller------------------
  246. // inputs
  247. wire [23:0] sdc_addr; // address to write or to start reading from
  248. wire [31:0] sdc_data; // data to write
  249. wire sdc_we; // write enable
  250. wire sdc_start; // start trigger
  251. // outputs
  252. wire [31:0] sdc_q; // memory output
  253. wire sdc_done; // output ready
  254. SDRAMcontroller sdramcontroller(
  255. // clock/reset inputs
  256. .clk (clk_SDRAM),
  257. .reset (reset),
  258. // interface inputs
  259. .sdc_addr (sdc_addr),
  260. .sdc_data (sdc_data),
  261. .sdc_we (sdc_we),
  262. .sdc_start (sdc_start),
  263. // interface outputs
  264. .sdc_q (sdc_q),
  265. .sdc_done (sdc_done),
  266. // SDRAM signals
  267. .SDRAM_CKE (SDRAM_CKE),
  268. .SDRAM_CSn (SDRAM_CSn),
  269. .SDRAM_WEn (SDRAM_WEn),
  270. .SDRAM_CASn (SDRAM_CASn),
  271. .SDRAM_RASn (SDRAM_RASn),
  272. .SDRAM_A (SDRAM_A),
  273. .SDRAM_BA (SDRAM_BA),
  274. .SDRAM_DQM (SDRAM_DQM),
  275. .SDRAM_DQ (SDRAM_DQ)
  276. );
  277. //---------------CPU----------------
  278. //CPU I/O
  279. wire [26:0] PC;
  280. CPU cpu(
  281. .clk (clk),
  282. .reset (reset),
  283. // bus
  284. .bus_addr (bus_addr),
  285. .bus_data (bus_data),
  286. .bus_we (bus_we),
  287. .bus_start (bus_start),
  288. .bus_q (bus_q),
  289. .bus_done (bus_done),
  290. // sdram bus
  291. .sdc_addr (sdc_addr),
  292. .sdc_data (sdc_data),
  293. .sdc_we (sdc_we),
  294. .sdc_start (sdc_start),
  295. .sdc_q (sdc_q),
  296. .sdc_done (sdc_done),
  297. .int1(int1),
  298. .int2(int2),
  299. .int3(int3),
  300. .int4(int4),
  301. .int5(int5),
  302. .int6(int6),
  303. .int7(int7),
  304. .int8(int8),
  305. .int9(int9),
  306. .int10(int10),
  307. .PC (PC)
  308. );
  309. //HDMI
  310. wire [3:0] TMDS_p;
  311. wire [3:0] TMDS_n;
  312. //SPI1
  313. wire SPI1_clk;
  314. wire SPI1_cs;
  315. wire SPI1_mosi;
  316. wire SPI1_miso;
  317. wire SPI1_rst;
  318. reg SPI1_nint;
  319. //SPI2
  320. wire SPI2_clk;
  321. wire SPI2_cs;
  322. wire SPI2_mosi;
  323. wire SPI2_miso;
  324. wire SPI2_rst;
  325. reg SPI2_nint;
  326. //SPI3
  327. wire SPI3_clk;
  328. wire SPI3_cs;
  329. wire SPI3_mosi;
  330. wire SPI3_miso;
  331. wire SPI3_nrst;
  332. reg SPI3_int;
  333. //SPI4
  334. wire SPI4_clk;
  335. wire SPI4_cs;
  336. wire SPI4_mosi;
  337. wire SPI4_miso;
  338. reg SPI4_gp;
  339. //UART0
  340. reg UART0_in;
  341. wire UART0_out;
  342. reg UART0_dtr;
  343. //UART1
  344. //reg UART1_in;
  345. //wire UART1_out;
  346. //UART2
  347. reg UART2_in;
  348. wire UART2_out;
  349. //PS/2
  350. reg PS2_clk;
  351. reg PS2_data;
  352. //Led
  353. wire led;
  354. //GPIO
  355. wire [3:0] GPO;
  356. reg [3:0] GPI;
  357. //DIP Switch
  358. reg [3:0] DIPS;
  359. //----------------Memory Unit--------------------
  360. //Memory Unit I/O
  361. //Interrupt signals
  362. wire OST1_int, OST2_int, OST3_int;
  363. wire UART0_rx_int, UART2_rx_int;
  364. wire PS2_int;
  365. wire SPI0_QSPI;
  366. MemoryUnit mu(
  367. //clock
  368. .clk (clk),
  369. .reset (reset),
  370. //CPU connection (Bus)
  371. .bus_addr (bus_addr),
  372. .bus_data (bus_data),
  373. .bus_we (bus_we),
  374. .bus_start (bus_start),
  375. .bus_q (bus_q),
  376. .bus_done (bus_done),
  377. /********
  378. * MEMORY
  379. ********/
  380. //SPI Flash / SPI0
  381. .SPIflash_data (SPI0_data),
  382. .SPIflash_q (SPI0_q),
  383. .SPIflash_wp (SPI0_wp),
  384. .SPIflash_hold (SPI0_hold),
  385. .SPIflash_cs (SPI0_cs),
  386. .SPIflash_clk (SPI0_clk),
  387. //VRAM32 cpu port
  388. .VRAM32_cpu_d (vram32_cpu_d),
  389. .VRAM32_cpu_addr (vram32_cpu_addr),
  390. .VRAM32_cpu_we (vram32_cpu_we),
  391. .VRAM32_cpu_q (vram32_cpu_q),
  392. //VRAM8 cpu port
  393. .VRAM8_cpu_d (vram8_cpu_d),
  394. .VRAM8_cpu_addr (vram8_cpu_addr),
  395. .VRAM8_cpu_we (vram8_cpu_we),
  396. .VRAM8_cpu_q (vram8_cpu_q),
  397. //VRAMspr cpu port
  398. .VRAMspr_cpu_d (vramSPR_cpu_d),
  399. .VRAMspr_cpu_addr (vramSPR_cpu_addr),
  400. .VRAMspr_cpu_we (vramSPR_cpu_we),
  401. .VRAMspr_cpu_q (vramSPR_cpu_q),
  402. //ROM
  403. .ROM_addr (rom_addr),
  404. .ROM_q (rom_q),
  405. /********
  406. * I/O
  407. ********/
  408. //UART0 (Main USB)
  409. .UART0_in (UART0_in),
  410. .UART0_out (UART0_out),
  411. .UART0_rx_interrupt (UART0_rx_int),
  412. //UART1 (APU)
  413. /*.UART1_in (),
  414. .UART1_out (),
  415. .UART1_rx_interrupt (),
  416. */
  417. //UART2 (GP)
  418. .UART2_in (UART2_in),
  419. .UART2_out (UART2_out),
  420. .UART2_rx_interrupt (UART2_rx_int),
  421. //SPI0 (Flash)
  422. //declared under MEMORY
  423. .SPI0_QSPI (SPI0_QSPI),
  424. //SPI1 (USB0/CH376T)
  425. .SPI1_clk (SPI1_clk),
  426. .SPI1_cs (SPI1_cs),
  427. .SPI1_mosi (SPI1_mosi),
  428. .SPI1_miso (SPI1_miso),
  429. .SPI1_nint (SPI1_nint_stable),
  430. //SPI2 (USB1/CH376T)
  431. .SPI2_clk (SPI2_clk),
  432. .SPI2_cs (SPI2_cs),
  433. .SPI2_mosi (SPI2_mosi),
  434. .SPI2_miso (SPI2_miso),
  435. .SPI2_nint (SPI2_nint_stable),
  436. //SPI3 (W5500)
  437. .SPI3_clk (SPI3_clk),
  438. .SPI3_cs (SPI3_cs),
  439. .SPI3_mosi (SPI3_mosi),
  440. .SPI3_miso (SPI3_miso),
  441. .SPI3_int (SPI3_int_stable),
  442. //SPI4 (EXT/GP)
  443. .SPI4_clk (SPI4_clk),
  444. .SPI4_cs (SPI4_cs),
  445. .SPI4_mosi (SPI4_mosi),
  446. .SPI4_miso (SPI4_miso),
  447. .SPI4_GP (SPI4_gp_stable),
  448. //GPIO (Separated GPI and GPO until GPIO module is implemented)
  449. .GPI (GPI[3:0]),
  450. .GPO (GPO[3:0]),
  451. //OStimers
  452. .OST1_int (OST1_int),
  453. .OST2_int (OST2_int),
  454. .OST3_int (OST3_int),
  455. //SNESpad
  456. /*
  457. .SNES_clk (),
  458. .SNES_latch (),
  459. .SNES_data (),
  460. */
  461. //PS/2
  462. .PS2_clk (PS2_clk),
  463. .PS2_data (PS2_data),
  464. .PS2_int (PS2_int), //Scan code ready signal
  465. //Boot mode
  466. .boot_mode (boot_mode_stable)
  467. );
  468. initial
  469. begin
  470. // dump everything for GTKwave
  471. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  472. $dumpvars;
  473. reset = 0;
  474. //repeat(5120) #10 clk = ~clk; // 50MHz
  475. repeat(4)
  476. begin
  477. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  478. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  479. end
  480. reset = 1;
  481. repeat(4)
  482. begin
  483. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  484. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  485. end
  486. reset = 0;
  487. repeat(22)
  488. begin
  489. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  490. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  491. end
  492. int1 = 1'b1;
  493. int2 = 1'b1;
  494. int3 = 1'b1;
  495. int4 = 1'b1;
  496. int5 = 1'b1;
  497. int6 = 1'b1;
  498. int7 = 1'b1;
  499. int8 = 1'b1;
  500. int9 = 1'b1;
  501. int10 = 1'b1;
  502. repeat(500)
  503. begin
  504. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  505. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  506. end
  507. int1 = 1'b0;
  508. int2 = 1'b0;
  509. int3 = 1'b0;
  510. int4 = 1'b0;
  511. int5 = 1'b0;
  512. int6 = 1'b0;
  513. int7 = 1'b0;
  514. int8 = 1'b0;
  515. int9 = 1'b0;
  516. int10 = 1'b0;
  517. repeat(100)
  518. begin
  519. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  520. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  521. end
  522. int1 = 1'b1;
  523. int2 = 1'b1;
  524. int3 = 1'b1;
  525. int4 = 1'b1;
  526. int5 = 1'b1;
  527. int6 = 1'b1;
  528. int7 = 1'b1;
  529. int8 = 1'b1;
  530. int9 = 1'b1;
  531. int10 = 1'b1;
  532. repeat(500)
  533. begin
  534. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  535. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  536. end
  537. /*
  538. repeat(4096)
  539. begin
  540. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  541. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  542. end
  543. */
  544. #1 $finish;
  545. end
  546. endmodule