clkMux_generation.rpt 4.8 KB

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  1. Info: Starting: Create simulation model
  2. Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation --family="Cyclone IV E" --part=EP4CE15F23C8
  3. Progress: Loading Quartus/clkMux.qsys
  4. Progress: Reading input file
  5. Progress: Adding altclkctrl_0 [altclkctrl 21.1]
  6. Progress: Parameterizing module altclkctrl_0
  7. Progress: Building connections
  8. Progress: Parameterizing connections
  9. Progress: Validating
  10. Progress: Done reading input file
  11. : clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
  12. : clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
  13. Info: clkMux: Generating clkMux "clkMux" for SIM_VERILOG
  14. Info: altclkctrl_0: Generating top-level entity clkMux_altclkctrl_0.
  15. Info: altclkctrl_0: "clkMux" instantiated altclkctrl "altclkctrl_0"
  16. Info: clkMux: Done "clkMux" with 2 modules, 2 files
  17. Info: qsys-generate succeeded.
  18. Info: Finished: Create simulation model
  19. Info: Starting: Create Modelsim Project.
  20. Info: sim-script-gen --spd=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/clkMux.spd --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ --use-relative-paths=true
  21. Info: Doing: ip-make-simscript --spd=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/clkMux.spd --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ --use-relative-paths=true
  22. Info: Generating the following file(s) for MODELSIM simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
  23. Info: mentor/msim_setup.tcl
  24. Info: Generating the following file(s) for VCS simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
  25. Info: synopsys/vcs/vcs_setup.sh
  26. Info: Generating the following file(s) for VCSMX simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
  27. Info: synopsys/vcsmx/synopsys_sim.setup
  28. Info: synopsys/vcsmx/vcsmx_setup.sh
  29. Info: Generating the following file(s) for NCSIM simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
  30. Info: cadence/cds.lib
  31. Info: cadence/hdl.var
  32. Info: cadence/ncsim_setup.sh
  33. Info: 1 .cds.lib files in cadence/cds_libs/ directory
  34. Info: Generating the following file(s) for RIVIERA simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
  35. Info: aldec/rivierapro_setup.tcl
  36. Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/.
  37. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
  38. Info: Finished: Create Modelsim Project.
  39. Info: Starting: Create block symbol file (.bsf)
  40. Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --block-symbol-file --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux --family="Cyclone IV E" --part=EP4CE15F23C8
  41. Progress: Loading Quartus/clkMux.qsys
  42. Progress: Reading input file
  43. Progress: Adding altclkctrl_0 [altclkctrl 21.1]
  44. Progress: Parameterizing module altclkctrl_0
  45. Progress: Building connections
  46. Progress: Parameterizing connections
  47. Progress: Validating
  48. Progress: Done reading input file
  49. : clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
  50. : clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
  51. Info: qsys-generate succeeded.
  52. Info: Finished: Create block symbol file (.bsf)
  53. Info:
  54. Info: Starting: Create HDL design files for synthesis
  55. Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --synthesis=VERILOG --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis --family="Cyclone IV E" --part=EP4CE15F23C8
  56. Progress: Loading Quartus/clkMux.qsys
  57. Progress: Reading input file
  58. Progress: Adding altclkctrl_0 [altclkctrl 21.1]
  59. Progress: Parameterizing module altclkctrl_0
  60. Progress: Building connections
  61. Progress: Parameterizing connections
  62. Progress: Validating
  63. Progress: Done reading input file
  64. : clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
  65. : clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
  66. Info: clkMux: Generating clkMux "clkMux" for QUARTUS_SYNTH
  67. Info: altclkctrl_0: Generating top-level entity clkMux_altclkctrl_0.
  68. Info: altclkctrl_0: "clkMux" instantiated altclkctrl "altclkctrl_0"
  69. Info: clkMux: Done "clkMux" with 2 modules, 2 files
  70. Info: qsys-generate succeeded.
  71. Info: Finished: Create HDL design files for synthesis