Info: Starting: Create simulation model
Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation --family="Cyclone IV E" --part=EP4CE15F23C8
Progress: Loading Quartus/clkMux.qsys
Progress: Reading input file
Progress: Adding altclkctrl_0 [altclkctrl 21.1]
Progress: Parameterizing module altclkctrl_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
: clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
: clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
Info: clkMux: Generating clkMux "clkMux" for SIM_VERILOG
Info: altclkctrl_0: Generating top-level entity clkMux_altclkctrl_0.
Info: altclkctrl_0: "clkMux" instantiated altclkctrl "altclkctrl_0"
Info: clkMux: Done "clkMux" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/clkMux.spd --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/clkMux.spd --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
Info: 	mentor/msim_setup.tcl
Info: Generating the following file(s) for VCS simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
Info: 	synopsys/vcs/vcs_setup.sh
Info: Generating the following file(s) for VCSMX simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
Info: 	synopsys/vcsmx/synopsys_sim.setup
Info: 	synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
Info: 	cadence/cds.lib
Info: 	cadence/hdl.var
Info: 	cadence/ncsim_setup.sh
Info: 	1 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --block-symbol-file --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux --family="Cyclone IV E" --part=EP4CE15F23C8
Progress: Loading Quartus/clkMux.qsys
Progress: Reading input file
Progress: Adding altclkctrl_0 [altclkctrl 21.1]
Progress: Parameterizing module altclkctrl_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
: clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
: clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --synthesis=VERILOG --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis --family="Cyclone IV E" --part=EP4CE15F23C8
Progress: Loading Quartus/clkMux.qsys
Progress: Reading input file
Progress: Adding altclkctrl_0 [altclkctrl 21.1]
Progress: Parameterizing module altclkctrl_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
: clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
: clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
Info: clkMux: Generating clkMux "clkMux" for QUARTUS_SYNTH
Info: altclkctrl_0: Generating top-level entity clkMux_altclkctrl_0.
Info: altclkctrl_0: "clkMux" instantiated altclkctrl "altclkctrl_0"
Info: clkMux: Done "clkMux" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis