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B32P.gtkw
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69e83fb855
Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline.
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2 년 전 |
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FPGC.gtkw
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9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
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6 달 전 |
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FPGC_50.gtkw
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9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
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6 달 전 |
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FSX.gtkw
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6e3cd7cd9c
PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs.
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1 년 전 |
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SDRAM.gtkw
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 년 전 |
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divider.gtkw
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f3f3a43044
Added fixed-point signed divider to MU. Integrated into FPCALC.
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1 년 전 |
bartpleiter
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.