lvds_bb.v 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172
  1. // megafunction wizard: %ALTIOBUF%VBB%
  2. // GENERATION: STANDARD
  3. // VERSION: WM1.0
  4. // MODULE: altiobuf_out
  5. // ============================================================
  6. // File Name: lvds.v
  7. // Megafunction Name(s):
  8. // altiobuf_out
  9. //
  10. // Simulation Library Files(s):
  11. //
  12. // ============================================================
  13. // ************************************************************
  14. // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  15. //
  16. // 21.1.1 Build 850 06/23/2022 SJ Lite Edition
  17. // ************************************************************
  18. //Copyright (C) 2022 Intel Corporation. All rights reserved.
  19. //Your use of Intel Corporation's design tools, logic functions
  20. //and other software and tools, and any partner logic
  21. //functions, and any output files from any of the foregoing
  22. //(including device programming or simulation files), and any
  23. //associated documentation or information are expressly subject
  24. //to the terms and conditions of the Intel Program License
  25. //Subscription Agreement, the Intel Quartus Prime License Agreement,
  26. //the Intel FPGA IP License Agreement, or other applicable license
  27. //agreement, including, without limitation, that your use is for
  28. //the sole purpose of programming logic devices manufactured by
  29. //Intel and sold by Intel or its authorized distributors. Please
  30. //refer to the applicable agreement for further details, at
  31. //https://fpgasoftware.intel.com/eula.
  32. module lvds (
  33. datain,
  34. dataout,
  35. dataout_b)/* synthesis synthesis_clearbox = 1 */;
  36. input [3:0] datain;
  37. output [3:0] dataout;
  38. output [3:0] dataout_b;
  39. endmodule
  40. // ============================================================
  41. // CNX file retrieval info
  42. // ============================================================
  43. // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
  44. // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
  45. // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
  46. // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
  47. // Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
  48. // Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
  49. // Retrieval info: CONSTANT: number_of_channels NUMERIC "4"
  50. // Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
  51. // Retrieval info: CONSTANT: pseudo_differential_mode STRING "FALSE"
  52. // Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
  53. // Retrieval info: CONSTANT: use_oe STRING "FALSE"
  54. // Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
  55. // Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL "datain[3..0]"
  56. // Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"
  57. // Retrieval info: USED_PORT: dataout_b 0 0 4 0 OUTPUT NODEFVAL "dataout_b[3..0]"
  58. // Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
  59. // Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
  60. // Retrieval info: CONNECT: dataout_b 0 0 4 0 @dataout_b 0 0 4 0
  61. // Retrieval info: GEN_FILE: TYPE_NORMAL lvds.v TRUE
  62. // Retrieval info: GEN_FILE: TYPE_NORMAL lvds.inc FALSE
  63. // Retrieval info: GEN_FILE: TYPE_NORMAL lvds.cmp FALSE
  64. // Retrieval info: GEN_FILE: TYPE_NORMAL lvds.bsf FALSE
  65. // Retrieval info: GEN_FILE: TYPE_NORMAL lvds_inst.v FALSE
  66. // Retrieval info: GEN_FILE: TYPE_NORMAL lvds_bb.v TRUE