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bart
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FPGC6
mirror of https://github.com/bartpleiter/FPGC6
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FPGC6
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Quartus
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clock_pll.qip

clock_pll.qip 436 B
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123456 
  1. set_global_assignment -name IP_TOOL_NAME "ALTPLL"
    2. 

  2. set_global_assignment -name IP_TOOL_VERSION "21.1"
    3. 

  3. set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
    4. 

  4. set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clock_pll.v"]
    5. 

  5. set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_pll_bb.v"]
    6. 

  6. set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_pll.ppf"]
    7.