FPGC6/Quartus/clock_pll.qip

set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "21.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clock_pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_pll_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_pll.ppf"]