Home Explore Help
Sign In
bart
/
FPGC6
mirror of https://github.com/bartpleiter/FPGC6
1
0
Fork 0
Files Issues 0 Wiki
Tree: 8d56c91fea
Branches Tags
FPGC6
/
Quartus
/
clkMux
/
synthesis
/
submodules
bart b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago
..
clkMux_altclkctrl_0.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago