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FPGC6
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FPGC6
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Assembler
bart 7e81e7fa17 Added files missing from last commit (L1I cache). 1 anno fa
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Bootloaders 7e81e7fa17 Added files missing from last commit (L1I cache). 1 anno fa
SimTests 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 anno fa
Assembler.py 7e81e7fa17 Added files missing from last commit (L1I cache). 1 anno fa
CompileInstruction.py 7e81e7fa17 Added files missing from last commit (L1I cache). 1 anno fa
buildToVerilog.sh 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 anno fa
compileAndSend.sh 1026f4776c Cleaned up some files 2 anni fa
simulate.sh 1026f4776c Cleaned up some files 2 anni fa