bart/FPGC6 @ 2fe0518bb364afe809c6f2774a64feeaa518ea75

bart 2fe0518bb3 Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.		преди 1 година
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clkMux	e1bb01a621 Cleaned and renamed Quartus project.	преди 1 година
clock_pll_v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clock_pll_v_sim	e1bb01a621 Cleaned and renamed Quartus project.	преди 1 година
memory	7e81e7fa17 Added files missing from last commit (L1I cache).	преди 1 година
modules	2fe0518bb3 Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.	преди 1 година
output_files	2fe0518bb3 Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.	преди 1 година
FPGC.qpf	e1bb01a621 Cleaned and renamed Quartus project.	преди 1 година
FPGC.qsf	add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.	преди 1 година
FPGC.qws	add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.	преди 1 година
FPGC.sdc	e1bb01a621 Cleaned and renamed Quartus project.	преди 1 година
NTSC_pll.ppf	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
NTSC_pll.qip	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	преди 2 години
NTSC_pll.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
NTSC_pll_bb.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clkMux.qsys	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clkMux.sopcinfo	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clock_pll.ppf	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clock_pll.qip	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	преди 2 години
clock_pll.v	308cc6a90d Fixed SDRAM controller by setting phase shift to 180 degrees.	преди 2 години
clock_pll_bb.v	308cc6a90d Fixed SDRAM controller by setting phase shift to 180 degrees.	преди 2 години
clock_pll_v.cmp	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clock_pll_v.qip	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clock_pll_v.sip	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clock_pll_v.spd	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
clock_pll_v.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
ddr.ppf	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
ddr.qip	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
ddr.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
ddr_bb.v	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	преди 2 години
output_file.cof	e1bb01a621 Cleaned and renamed Quartus project.	преди 1 година