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4 Atzari

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bart 2287e54c6b Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.		1 gadu atpakaļ
Assembler	7e81e7fa17 Added files missing from last commit (L1I cache).	1 gadu atpakaļ
BCC	52f2819774 Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.	1 gadu atpakaļ
Documentation	9a285550c0 Updated documentation a bit, added newlines to BENCH, removed wrong comments from L2cache.v	1 gadu atpakaļ
Graphics	c4599a63cc New documentation structure. Updated some documentation. Added relevant graphics scripts and files from FPGC5 repo.	2 gadi atpakaļ
Programmer	52f2819774 Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.	1 gadu atpakaļ
Quartus	2287e54c6b Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.	1 gadu atpakaļ
SublimeText3	1026f4776c Cleaned up some files	2 gadi atpakaļ
Verilog	2287e54c6b Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.	1 gadu atpakaļ
.gitattributes	b9bc26129d Added gitattributes to ignore the huge UARTbootloader.asm file. Deleted old quartus test project.	2 gadi atpakaļ
.gitignore	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 gadi atpakaļ
LICENSE.txt	9ec3298860 Updated README and added licence so repo can go public now	2 gadi atpakaļ
README.md	3d9b4194f7 Added initial documentation	2 gadi atpakaļ

FPGC6