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bart
/
FPGC6
mirrorاز https://github.com/bartpleiter/FPGC6
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درخت: 2287e54c6b
شاخه‌ها تگ‌ها
FPGC6
/
Quartus
bart 2287e54c6b Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM. 1 سال پیش
..
clkMux e1bb01a621 Cleaned and renamed Quartus project. 2 سال پیش
clock_pll_v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v_sim e1bb01a621 Cleaned and renamed Quartus project. 2 سال پیش
memory 7e81e7fa17 Added files missing from last commit (L1I cache). 1 سال پیش
modules 2287e54c6b Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM. 1 سال پیش
output_files 2fe0518bb3 Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader. 1 سال پیش
FPGC.qpf e1bb01a621 Cleaned and renamed Quartus project. 2 سال پیش
FPGC.qsf add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing. 1 سال پیش
FPGC.qws 2287e54c6b Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM. 1 سال پیش
FPGC.sdc e1bb01a621 Cleaned and renamed Quartus project. 2 سال پیش
NTSC_pll.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
NTSC_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 سال پیش
NTSC_pll.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
NTSC_pll_bb.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clkMux.qsys a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clkMux.sopcinfo a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 سال پیش
clock_pll.v 308cc6a90d Fixed SDRAM controller by setting phase shift to 180 degrees. 2 سال پیش
clock_pll_bb.v 308cc6a90d Fixed SDRAM controller by setting phase shift to 180 degrees. 2 سال پیش
clock_pll_v.cmp a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.sip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.spd a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
clock_pll_v.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr.ppf a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr.qip a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
ddr_bb.v a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. 2 سال پیش
output_file.cof e1bb01a621 Cleaned and renamed Quartus project. 2 سال پیش