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clkMux
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e1bb01a621
Cleaned and renamed Quartus project.
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2 years ago |
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clock_pll_v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clock_pll_v_sim
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e1bb01a621
Cleaned and renamed Quartus project.
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2 years ago |
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memory
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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modules
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2287e54c6b
Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.
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1 year ago |
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output_files
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2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
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1 year ago |
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FPGC.qpf
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e1bb01a621
Cleaned and renamed Quartus project.
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2 years ago |
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FPGC.qsf
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 year ago |
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FPGC.qws
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2287e54c6b
Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.
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1 year ago |
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FPGC.sdc
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e1bb01a621
Cleaned and renamed Quartus project.
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2 years ago |
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NTSC_pll.ppf
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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NTSC_pll.qip
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 years ago |
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NTSC_pll.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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NTSC_pll_bb.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clkMux.qsys
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clkMux.sopcinfo
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clock_pll.ppf
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clock_pll.qip
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 years ago |
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clock_pll.v
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308cc6a90d
Fixed SDRAM controller by setting phase shift to 180 degrees.
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2 years ago |
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clock_pll_bb.v
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308cc6a90d
Fixed SDRAM controller by setting phase shift to 180 degrees.
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2 years ago |
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clock_pll_v.cmp
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clock_pll_v.qip
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clock_pll_v.sip
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clock_pll_v.spd
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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clock_pll_v.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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ddr.ppf
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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ddr.qip
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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ddr.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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ddr_bb.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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output_file.cof
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e1bb01a621
Cleaned and renamed Quartus project.
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2 years ago |
bart
2287e54c6b
Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.