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L1Dcache.v
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 rok pred |
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L1DcacheUnstable.v
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 rok pred |
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L1Icache.v
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 rok pred |
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L1IcacheUnstable.v
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 rok pred |
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L2cache.v
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f78729ea77
Fixed L2 cache state machine issue which was only present in the previous commit.
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1 rok pred |
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MemoryUnit.v
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9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
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6 mesiacov pred |
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ROM.v
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 rokov pred |
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SDRAMcontroller.v
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 rok pred |
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SPIreader.v
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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2 rokov pred |
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SRAM.v
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9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
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6 mesiacov pred |
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VRAM.v
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6dc8fc396f
Added Pixel Engine in simulation.
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2 rokov pred |
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mt48lc16m16a2.v
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442d51ba85
Added images to documentation, HDMI is working without lvds, init of new sdram controller done.
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2 rokov pred |
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w25q128jv.v
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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2 rokov pred |
bartpleiter
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.