bartpleiter 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. vor 5 Monaten
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L1Dcache.v add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing. vor 1 Jahr
L1DcacheUnstable.v add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing. vor 1 Jahr
L1Icache.v add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing. vor 1 Jahr
L1IcacheUnstable.v add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing. vor 1 Jahr
L2cache.v f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. vor 1 Jahr
MemoryUnit.v 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. vor 5 Monaten
ROM.v 55f619efae Initial commit with some empty Verilog template code from FPGC5 vor 2 Jahren
SDRAMcontroller.v 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. vor 1 Jahr
SPIreader.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design vor 2 Jahren
SRAM.v 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. vor 5 Monaten
VRAM.v 6dc8fc396f Added Pixel Engine in simulation. vor 1 Jahr
mt48lc16m16a2.v 442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done. vor 2 Jahren
w25q128jv.v 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design vor 2 Jahren