提交歷史

作者 SHA1 備註 提交日期
  bart 7e81e7fa17 Added files missing from last commit (L1I cache). 1 年之前
  bart 69e83fb855 Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline. 2 年之前
  Bart e5dd555fdb Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation. 2 年之前
  Bart 9da01544e7 Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well 2 年之前
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. 2 年之前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年之前