 bart
|
7e81e7fa17
Added files missing from last commit (L1I cache).
|
преди 1 година |
|
bart
|
69e83fb855
Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline.
|
преди 2 години |
|
Bart
|
e5dd555fdb
Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.
|
преди 2 години |
|
Bart
|
9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
|
преди 2 години |
|
Bart
|
a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
|
преди 2 години |
|
Bart
|
55f619efae
Initial commit with some empty Verilog template code from FPGC5
|
преди 2 години |
